Patchwork [1/7] ARM: tegra: add ac97 clock

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Submitter Lucas Stach
Date Dec. 19, 2012, 11:17 p.m.
Message ID <1355959056-6009-1-git-send-email-dev@lynxeye.de>
Download mbox | patch
Permalink /patch/207541/
State Not Applicable, archived
Headers show

Comments

Lucas Stach - Dec. 19, 2012, 11:17 p.m.
Add clock used by the AC97 host controller.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/mach-tegra/board-dt-tegra20.c    | 2 ++
 arch/arm/mach-tegra/tegra20_clocks_data.c | 2 ++
 2 Dateien geändert, 4 Zeilen hinzugefügt(+)
Stephen Warren - Dec. 20, 2012, 7:24 p.m.
On 12/19/2012 04:17 PM, Lucas Stach wrote:
> Add clock used by the AC97 host controller.

This is going to conflict with Prashant's clock driver rework. Can you
rebase it on top of that once it's checked in. That might be a couple
weeks out though.
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Patch

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 734d9cc..acff2bd 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -78,6 +78,7 @@  struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-ac97", TEGRA_AC97_BASE, "tegra20-ac97", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
@@ -114,6 +115,7 @@  static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	{ "pll_a_out0", "pll_a",        11289600,       true },
 	{ "cdev1",      NULL,           0,              true },
 	{ "blink",      "clk_32k",      32768,          true },
+	{ "ac97",       "pll_a_out0",   24576000,       false},
 	{ "i2s1",       "pll_a_out0",   11289600,       false},
 	{ "i2s2",       "pll_a_out0",   11289600,       false},
 	{ "sdmmc1",	"pll_p",	48000000,	false},
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index a23a073..33f1230 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -891,6 +891,7 @@  DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
 PERIPH_CLK(apbdma,	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0);
 PERIPH_CLK(rtc,		"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET);
 PERIPH_CLK(timer,	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0);
+PERIPH_CLK(ac97,	"tegra20-ac97",		NULL,	3,	0,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	DIV_U71);
 PERIPH_CLK(i2s1,	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
 PERIPH_CLK(i2s2,	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
 PERIPH_CLK(spdif_out,	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71);
@@ -957,6 +958,7 @@  static struct clk *tegra_list_clks[] = {
 	&tegra_apbdma,
 	&tegra_rtc,
 	&tegra_timer,
+	&tegra_ac97,
 	&tegra_i2s1,
 	&tegra_i2s2,
 	&tegra_spdif_out,