| Message ID | 1355887399-21212-1-git-send-email-prabhakar@freescale.com |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andy Fleming |
| Headers | show |
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index d58c24c..d93e026 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -259,7 +259,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's Address Mask Registers is initialised 64K size. So Fix the Address Mask Register initilisation as 4K Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> --- Changes for v2: - Spaces around binary operators include/configs/t4qds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)