[U-Boot] board/T4240qds:Fix TLB and LAW size of NAND flash

Submitted by Prabhakar Kushwaha on Dec. 18, 2012, 10:15 a.m.

Details

Message ID 1355825745-29101-1-git-send-email-prabhakar@freescale.com
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Commit Message

Prabhakar Kushwaha Dec. 18, 2012, 10:15 a.m.
The internal SRAM of Freescale's IFC NAND machine is of 64K and controller's
Address Mask Registers is initialised with the same.

So Update TLB and LAW size of NAND flash accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 board/freescale/t4qds/law.c |    2 +-
 board/freescale/t4qds/tlb.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 5debcf6..6f2c5c8 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -40,7 +40,7 @@  struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
 #endif
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 #endif
 };
 
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 078a6e4..80eb511 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -125,7 +125,7 @@  struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 16, BOOKE_PAGESZ_1M, 1),
+			0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
 	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,