Patchwork ARM: tegra: dynamically calculate pll_d parameters

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Submitter Lucas Stach
Date Dec. 17, 2012, 5:58 p.m.
Message ID <1355767103-5303-1-git-send-email-dev@lynxeye.de>
Download mbox | patch
Permalink /patch/206949/
State Rejected, archived
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Comments

Lucas Stach - Dec. 17, 2012, 5:58 p.m.
Calculate PLL_D parameters in a dynamically instead of using a fixed
table. This allows TegraDRM to drive outputs with CVT compliant modes.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
Maybe we can generalize this a bit and reuse this for other PLLs. But
for now the calculation is specific to PLL_D. To make this useable for
other PLLs we need to push cpcon and valid P values into the structure
that defines a PLL.
---
 arch/arm/mach-tegra/tegra20_clocks.c      | 88 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/tegra20_clocks.h      |  1 +
 arch/arm/mach-tegra/tegra20_clocks_data.c | 28 +---------
 3 Dateien geändert, 91 Zeilen hinzugefügt(+), 26 Zeilen entfernt(-)
Stephen Warren - Dec. 17, 2012, 10:01 p.m.
On 12/17/2012 10:58 AM, Lucas Stach wrote:
> Calculate PLL_D parameters in a dynamically instead of using a fixed
> table. This allows TegraDRM to drive outputs with CVT compliant modes.

Prashant, can you please review this, and comment on the best approach
for dealing with the conflict this has with your clock driver rework.
Thanks.

Lucas, I assume this algorithm generates the same cpcon values (and
indeed M/N/P values) as were in the fixed pll_d_freq_table before?
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Lucas Stach - Dec. 17, 2012, 10:16 p.m.
Am Montag, den 17.12.2012, 15:01 -0700 schrieb Stephen Warren:
> On 12/17/2012 10:58 AM, Lucas Stach wrote:
> > Calculate PLL_D parameters in a dynamically instead of using a fixed
> > table. This allows TegraDRM to drive outputs with CVT compliant modes.
> 
> Prashant, can you please review this, and comment on the best approach
> for dealing with the conflict this has with your clock driver rework.
> Thanks.
> 
> Lucas, I assume this algorithm generates the same cpcon values (and
> indeed M/N/P values) as were in the fixed pll_d_freq_table before?
> 
I know this might not be the nicest thing for validation, but no this
isn't generating exactly the same values. The tables used a fixed 1MHz
Cf, which results in high N values for faster pixel clocks. The new
algorithm tries to use a higher Cf if possible, resulting in smaller N
which provides the opportunity to reduce cpcon, which in turn might be a
win for power consumption.

The cpcon values are set according to the TRM and are indeed the same
when using Cf=1MHz.

To match the old behaviour of the table I would have to further dumb
down the calculation, which might make this more specific to PLL_D and
reduce the possibility to reuse parts of the code for other PLLs later
on. But as apparently there's a rework going on this might not be an
relevant argument.

Regards,
Lucas

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Prashant Gaikwad - Dec. 18, 2012, 5:45 a.m.
On Tuesday 18 December 2012 03:31 AM, Stephen Warren wrote:
> On 12/17/2012 10:58 AM, Lucas Stach wrote:
>> Calculate PLL_D parameters in a dynamically instead of using a fixed
>> table. This allows TegraDRM to drive outputs with CVT compliant modes.
> Prashant, can you please review this, and comment on the best approach
> for dealing with the conflict this has with your clock driver rework.
> Thanks.
>
> Lucas, I assume this algorithm generates the same cpcon values (and
> indeed M/N/P values) as were in the fixed pll_d_freq_table before?

Stephen,

My clock driver rework includes automatic rate calculation if expected 
entry is not found in tables.

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Thierry Reding - Dec. 18, 2012, 6:58 a.m.
On Mon, Dec 17, 2012 at 06:58:23PM +0100, Lucas Stach wrote:
[...]
> +static int tegra20_plld_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> +		unsigned long parent_rate)
> +{
> +	struct clk_tegra *c = to_clk_tegra(hw);
> +	unsigned long input_rate = parent_rate;
> +	u64 n = 0;
> +	int m_max, m_min, m = 0;
> +	u32 val, rem = 0;
> +	u8 cpcon = 0;
> +
> +	m_max = input_rate / c->u.pll.cf_min;
> +	m_min = (input_rate / c->u.pll.cf_max) + 1;
> +
> +	for (m = m_min; m <= m_max; m++) {
> +		n = (u64)rate * m;
> +		rem = do_div(n, input_rate);
> +		if (!rem)
> +			break;
> +	}
> +
> +	if (rem)
> +		return -EINVAL;

This code is common to both .round_rate() and .set_rate() so maybe you
should factor it out.

> +
> +	c->mul = n;
> +	c->div = n;
> +
> +	val = clk_readl(c->reg + PLL_BASE);
> +	val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
> +		 PLL_BASE_DIVM_MASK);
> +	val |= (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT);
> +	clk_writel(val, c->reg + PLL_BASE);
> +
> +	if (n <= 50)
> +		cpcon = 2;
> +	else if (n <= 300)
> +		cpcon = 4;
> +	else if (n <= 600)
> +		cpcon = 8;
> +	else if (n <= 1000)
> +		cpcon = 12;
> +
> +	val = clk_readl(c->reg + PLL_MISC(c));
> +	val &= ~PLL_MISC_CPCON_MASK;
> +	val |= cpcon << PLL_MISC_CPCON_SHIFT;
> +	clk_writel(val, c->reg + PLL_MISC(c));
> +
> +

There's a gratuitous blank line here.

Other than that this algorithm looks pretty much like what I came up
with in an earlier prototype. One difference is that I used an
additional outer loop for the p-divider. Taking that into account should
allow even more frequencies to be matched.

Thierry
Mark Zhang - Dec. 18, 2012, 8:36 a.m.
I think we don't need to define a pll_ops for every individual pll.
That'll be redundant. Just use one pll_ops(with parameter dynamically
calculating) which is able to serve several plls is OK. Refer to
tegra30_clocks_data.c, it has already implemented this.

Mark
On 12/18/2012 01:58 AM, Lucas Stach wrote:
> Calculate PLL_D parameters in a dynamically instead of using a fixed
> table. This allows TegraDRM to drive outputs with CVT compliant modes.
> 
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> Maybe we can generalize this a bit and reuse this for other PLLs. But
> for now the calculation is specific to PLL_D. To make this useable for
> other PLLs we need to push cpcon and valid P values into the structure
> that defines a PLL.
> ---
>  arch/arm/mach-tegra/tegra20_clocks.c      | 88 +++++++++++++++++++++++++++++++
>  arch/arm/mach-tegra/tegra20_clocks.h      |  1 +
>  arch/arm/mach-tegra/tegra20_clocks_data.c | 28 +---------
>  3 Dateien geändert, 91 Zeilen hinzugefügt(+), 26 Zeilen entfernt(-)
> 
> diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
> index 4eb6bc8..04b0ff59 100644
> --- a/arch/arm/mach-tegra/tegra20_clocks.c
> +++ b/arch/arm/mach-tegra/tegra20_clocks.c
> @@ -894,6 +894,94 @@ struct clk_ops tegra_plle_ops = {
>  	.round_rate = tegra20_pll_clk_round_rate,
>  };
>  
> +static int tegra20_plld_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> +		unsigned long parent_rate)
> +{
> +	struct clk_tegra *c = to_clk_tegra(hw);
> +	unsigned long input_rate = parent_rate;
> +	u64 n = 0;
> +	int m_max, m_min, m = 0;
> +	u32 val, rem = 0;
> +	u8 cpcon = 0;
> +
> +	m_max = input_rate / c->u.pll.cf_min;
> +	m_min = (input_rate / c->u.pll.cf_max) + 1;
> +
> +	for (m = m_min; m <= m_max; m++) {
> +		n = (u64)rate * m;
> +		rem = do_div(n, input_rate);
> +		if (!rem)
> +			break;
> +	}
> +
> +	if (rem)
> +		return -EINVAL;
> +
> +	c->mul = n;
> +	c->div = n;
> +
> +	val = clk_readl(c->reg + PLL_BASE);
> +	val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
> +		 PLL_BASE_DIVM_MASK);
> +	val |= (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT);
> +	clk_writel(val, c->reg + PLL_BASE);
> +
> +	if (n <= 50)
> +		cpcon = 2;
> +	else if (n <= 300)
> +		cpcon = 4;
> +	else if (n <= 600)
> +		cpcon = 8;
> +	else if (n <= 1000)
> +		cpcon = 12;
> +
> +	val = clk_readl(c->reg + PLL_MISC(c));
> +	val &= ~PLL_MISC_CPCON_MASK;
> +	val |= cpcon << PLL_MISC_CPCON_SHIFT;
> +	clk_writel(val, c->reg + PLL_MISC(c));
> +
> +
> +	if (c->state == ON)
> +		tegra20_pll_clk_enable(hw);
> +
> +	return 0;
> +}
> +
> +static long tegra20_plld_clk_round_rate(struct clk_hw *hw, unsigned long rate,
> +				unsigned long *prate)
> +{
> +	struct clk_tegra *c = to_clk_tegra(hw);
> +	unsigned long input_rate = *prate;
> +	u64 n;
> +	u32 rem;
> +	int m_max, m_min, m;
> +
> +	if (rate < c->u.pll.vco_min || rate > c->u.pll.vco_max)
> +		return -EINVAL;
> +
> +	m_max = input_rate / c->u.pll.cf_min;
> +	m_min = (input_rate / c->u.pll.cf_max) + 1;
> +
> +	/* check if we can find an matching integer N */
> +	for (m = m_min; m <= m_max; m++) {
> +		n = (u64)rate * m;
> +		rem = do_div(n, input_rate);
> +		if (!rem)
> +			return rate;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +struct clk_ops tegra_plld_ops = {
> +	.is_enabled = tegra20_pll_clk_is_enabled,
> +	.enable = tegra20_pll_clk_enable,
> +	.disable = tegra20_pll_clk_disable,
> +	.set_rate = tegra20_plld_clk_set_rate,
> +	.recalc_rate = tegra20_pll_clk_recalc_rate,
> +	.round_rate = tegra20_plld_clk_round_rate,
> +};
> +
>  /* Clock divider ops */
>  static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
>  {
> diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
> index 8bfd31b..b7bfe87 100644
> --- a/arch/arm/mach-tegra/tegra20_clocks.h
> +++ b/arch/arm/mach-tegra/tegra20_clocks.h
> @@ -21,6 +21,7 @@ extern struct clk_ops tegra_clk_32k_ops;
>  extern struct clk_ops tegra_pll_ops;
>  extern struct clk_ops tegra_clk_m_ops;
>  extern struct clk_ops tegra_pll_div_ops;
> +extern struct clk_ops tegra_plld_ops;
>  extern struct clk_ops tegra_pllx_ops;
>  extern struct clk_ops tegra_plle_ops;
>  extern struct clk_ops tegra_clk_double_ops;
> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
> index a23a073..5a190ec 100644
> --- a/arch/arm/mach-tegra/tegra20_clocks_data.c
> +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
> @@ -240,33 +240,9 @@ DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
>  DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
>  		tegra_pll_div_ops, pll_a, 0);
>  
> -static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
> -	{ 12000000, 216000000, 216, 12, 1, 4},
> -	{ 13000000, 216000000, 216, 13, 1, 4},
> -	{ 19200000, 216000000, 135, 12, 1, 3},
> -	{ 26000000, 216000000, 216, 26, 1, 4},
> -
> -	{ 12000000, 297000000,  99,  4, 1, 4 },
> -	{ 12000000, 339000000, 113,  4, 1, 4 },
> -
> -	{ 12000000, 594000000, 594, 12, 1, 8},
> -	{ 13000000, 594000000, 594, 13, 1, 8},
> -	{ 19200000, 594000000, 495, 16, 1, 8},
> -	{ 26000000, 594000000, 594, 26, 1, 8},
> -
> -	{ 12000000, 616000000, 616, 12, 1, 8},
> -
> -	{ 12000000, 1000000000, 1000, 12, 1, 12},
> -	{ 13000000, 1000000000, 1000, 13, 1, 12},
> -	{ 19200000, 1000000000, 625,  12, 1, 8},
> -	{ 26000000, 1000000000, 1000, 26, 1, 12},
> -
> -	{ 0, 0, 0, 0, 0, 0 },
> -};
> -
>  DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
> -		1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
> -		1000, tegra_pll_ops, 0, clk_m);
> +		1000000, 6000000, 40000000, 1000000000, NULL,
> +		1000, tegra_plld_ops, 0, clk_m);
>  
>  DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
>  		tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
> 
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Lucas Stach - Dec. 18, 2012, 8:40 a.m.
Am Dienstag, den 18.12.2012, 07:58 +0100 schrieb Thierry Reding:
> On Mon, Dec 17, 2012 at 06:58:23PM +0100, Lucas Stach wrote:
> [...]
> > +static int tegra20_plld_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> > +		unsigned long parent_rate)
> > +{
> > +	struct clk_tegra *c = to_clk_tegra(hw);
> > +	unsigned long input_rate = parent_rate;
> > +	u64 n = 0;
> > +	int m_max, m_min, m = 0;
> > +	u32 val, rem = 0;
> > +	u8 cpcon = 0;
> > +
> > +	m_max = input_rate / c->u.pll.cf_min;
> > +	m_min = (input_rate / c->u.pll.cf_max) + 1;
> > +
> > +	for (m = m_min; m <= m_max; m++) {
> > +		n = (u64)rate * m;
> > +		rem = do_div(n, input_rate);
> > +		if (!rem)
> > +			break;
> > +	}
> > +
> > +	if (rem)
> > +		return -EINVAL;
> 
> This code is common to both .round_rate() and .set_rate() so maybe you
> should factor it out.
> 
Right.

> > +
> > +	c->mul = n;
> > +	c->div = n;
> > +
> > +	val = clk_readl(c->reg + PLL_BASE);
> > +	val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
> > +		 PLL_BASE_DIVM_MASK);
> > +	val |= (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT);
> > +	clk_writel(val, c->reg + PLL_BASE);
> > +
> > +	if (n <= 50)
> > +		cpcon = 2;
> > +	else if (n <= 300)
> > +		cpcon = 4;
> > +	else if (n <= 600)
> > +		cpcon = 8;
> > +	else if (n <= 1000)
> > +		cpcon = 12;
> > +
> > +	val = clk_readl(c->reg + PLL_MISC(c));
> > +	val &= ~PLL_MISC_CPCON_MASK;
> > +	val |= cpcon << PLL_MISC_CPCON_SHIFT;
> > +	clk_writel(val, c->reg + PLL_MISC(c));
> > +
> > +
> 
> There's a gratuitous blank line here.
> 
> Other than that this algorithm looks pretty much like what I came up
> with in an earlier prototype. One difference is that I used an
> additional outer loop for the p-divider. Taking that into account should
> allow even more frequencies to be matched.

I don't think the outer loop is needed. The Coordinated Video Timings
(CVT) spec demands that pixelclocks are always aligned to 0.25MHz. As we
are running pll_d at four times the pixel clock we are always hitting a
plain integer value for the pll_d MHz.

Regards,
Lucas

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Lucas Stach - Dec. 18, 2012, 9:19 a.m.
Am Dienstag, den 18.12.2012, 16:36 +0800 schrieb Mark Zhang:
> I think we don't need to define a pll_ops for every individual pll.
> That'll be redundant. Just use one pll_ops(with parameter dynamically
> calculating) which is able to serve several plls is OK. Refer to
> tegra30_clocks_data.c, it has already implemented this.
> 
This would be the right thing to do in the long run. But PLL_D requires
a lot less complexity than others to compute the PLL values, because of
the constraints that could be applied. That's why I started doing a
simple function to only make PLL_D dynamic.

I could certainly go ahead and come up with something which applies to
all PLLs, but I imagine this might be even a bigger validation hassle
for NVidia.

Also I'm still not sure how much this patch collides with the clock
rework. I don't know how far this rework has progressed already and I
would like to avoid doing redundant work. Prashant could you please
clarify?

Regards,
Lucas

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Stephen Warren - Dec. 18, 2012, 4:40 p.m.
On 12/18/2012 02:19 AM, Lucas Stach wrote:
> Am Dienstag, den 18.12.2012, 16:36 +0800 schrieb Mark Zhang:
>> I think we don't need to define a pll_ops for every individual pll.
>> That'll be redundant. Just use one pll_ops(with parameter dynamically
>> calculating) which is able to serve several plls is OK. Refer to
>> tegra30_clocks_data.c, it has already implemented this.
>>
> This would be the right thing to do in the long run. But PLL_D requires
> a lot less complexity than others to compute the PLL values, because of
> the constraints that could be applied. That's why I started doing a
> simple function to only make PLL_D dynamic.
> 
> I could certainly go ahead and come up with something which applies to
> all PLLs, but I imagine this might be even a bigger validation hassle
> for NVidia.
> 
> Also I'm still not sure how much this patch collides with the clock
> rework. I don't know how far this rework has progressed already and I
> would like to avoid doing redundant work. Prashant could you please
> clarify?

The code is moved to drivers/clk/tegra/, and split up into
per-clock-type files, rather than a single monolithic clock type.
There's basically zero possibility to merge anything across that
transition; a patch would need to be rebased (well, more like manually
re-written) to be applicable.

I hope it won't be more than a day or two before Prashant posts his
patches...
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Patch

diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 4eb6bc8..04b0ff59 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -894,6 +894,94 @@  struct clk_ops tegra_plle_ops = {
 	.round_rate = tegra20_pll_clk_round_rate,
 };
 
+static int tegra20_plld_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long parent_rate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long input_rate = parent_rate;
+	u64 n = 0;
+	int m_max, m_min, m = 0;
+	u32 val, rem = 0;
+	u8 cpcon = 0;
+
+	m_max = input_rate / c->u.pll.cf_min;
+	m_min = (input_rate / c->u.pll.cf_max) + 1;
+
+	for (m = m_min; m <= m_max; m++) {
+		n = (u64)rate * m;
+		rem = do_div(n, input_rate);
+		if (!rem)
+			break;
+	}
+
+	if (rem)
+		return -EINVAL;
+
+	c->mul = n;
+	c->div = n;
+
+	val = clk_readl(c->reg + PLL_BASE);
+	val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+		 PLL_BASE_DIVM_MASK);
+	val |= (m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT);
+	clk_writel(val, c->reg + PLL_BASE);
+
+	if (n <= 50)
+		cpcon = 2;
+	else if (n <= 300)
+		cpcon = 4;
+	else if (n <= 600)
+		cpcon = 8;
+	else if (n <= 1000)
+		cpcon = 12;
+
+	val = clk_readl(c->reg + PLL_MISC(c));
+	val &= ~PLL_MISC_CPCON_MASK;
+	val |= cpcon << PLL_MISC_CPCON_SHIFT;
+	clk_writel(val, c->reg + PLL_MISC(c));
+
+
+	if (c->state == ON)
+		tegra20_pll_clk_enable(hw);
+
+	return 0;
+}
+
+static long tegra20_plld_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *prate)
+{
+	struct clk_tegra *c = to_clk_tegra(hw);
+	unsigned long input_rate = *prate;
+	u64 n;
+	u32 rem;
+	int m_max, m_min, m;
+
+	if (rate < c->u.pll.vco_min || rate > c->u.pll.vco_max)
+		return -EINVAL;
+
+	m_max = input_rate / c->u.pll.cf_min;
+	m_min = (input_rate / c->u.pll.cf_max) + 1;
+
+	/* check if we can find an matching integer N */
+	for (m = m_min; m <= m_max; m++) {
+		n = (u64)rate * m;
+		rem = do_div(n, input_rate);
+		if (!rem)
+			return rate;
+	}
+
+	return -EINVAL;
+}
+
+struct clk_ops tegra_plld_ops = {
+	.is_enabled = tegra20_pll_clk_is_enabled,
+	.enable = tegra20_pll_clk_enable,
+	.disable = tegra20_pll_clk_disable,
+	.set_rate = tegra20_plld_clk_set_rate,
+	.recalc_rate = tegra20_pll_clk_recalc_rate,
+	.round_rate = tegra20_plld_clk_round_rate,
+};
+
 /* Clock divider ops */
 static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
index 8bfd31b..b7bfe87 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -21,6 +21,7 @@  extern struct clk_ops tegra_clk_32k_ops;
 extern struct clk_ops tegra_pll_ops;
 extern struct clk_ops tegra_clk_m_ops;
 extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
 extern struct clk_ops tegra_pllx_ops;
 extern struct clk_ops tegra_plle_ops;
 extern struct clk_ops tegra_clk_double_ops;
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index a23a073..5a190ec 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -240,33 +240,9 @@  DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
 		tegra_pll_div_ops, pll_a, 0);
 
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-	{ 12000000, 216000000, 216, 12, 1, 4},
-	{ 13000000, 216000000, 216, 13, 1, 4},
-	{ 19200000, 216000000, 135, 12, 1, 3},
-	{ 26000000, 216000000, 216, 26, 1, 4},
-
-	{ 12000000, 297000000,  99,  4, 1, 4 },
-	{ 12000000, 339000000, 113,  4, 1, 4 },
-
-	{ 12000000, 594000000, 594, 12, 1, 8},
-	{ 13000000, 594000000, 594, 13, 1, 8},
-	{ 19200000, 594000000, 495, 16, 1, 8},
-	{ 26000000, 594000000, 594, 26, 1, 8},
-
-	{ 12000000, 616000000, 616, 12, 1, 8},
-
-	{ 12000000, 1000000000, 1000, 12, 1, 12},
-	{ 13000000, 1000000000, 1000, 13, 1, 12},
-	{ 19200000, 1000000000, 625,  12, 1, 8},
-	{ 26000000, 1000000000, 1000, 26, 1, 12},
-
-	{ 0, 0, 0, 0, 0, 0 },
-};
-
 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
-		1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
-		1000, tegra_pll_ops, 0, clk_m);
+		1000000, 6000000, 40000000, 1000000000, NULL,
+		1000, tegra_plld_ops, 0, clk_m);
 
 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
 		tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);