From patchwork Mon Dec 17 12:08:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 206844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A8ECE2C0093 for ; Mon, 17 Dec 2012 23:09:44 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752662Ab2LQMJG (ORCPT ); Mon, 17 Dec 2012 07:09:06 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:4906 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752298Ab2LQMJE (ORCPT ); Mon, 17 Dec 2012 07:09:04 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Mon, 17 Dec 2012 04:08:18 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 17 Dec 2012 04:06:27 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 17 Dec 2012 04:06:27 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Mon, 17 Dec 2012 04:08:37 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Mon, 17 Dec 2012 04:08:50 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qBHC8SxY014291; Mon, 17 Dec 2012 04:08:36 -0800 (PST) From: Laxman Dewangan To: CC: , , , Laxman Dewangan Subject: [PATCH 3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt Date: Mon, 17 Dec 2012 17:38:20 +0530 Message-ID: <1355746101-15291-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1355746101-15291-1-git-send-email-ldewangan@nvidia.com> References: <1355746101-15291-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add OF_DEV_AUXDATA for high speed uart controller driver for Tegra20/Tegra30 board dt files. Set the parent clock of uart controller to PLLP. Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++++++ arch/arm/mach-tegra/board-dt-tegra30.c | 9 +++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 734d9cc..959c8b3 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL), OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL), OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL), OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL), OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL), OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL), @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 216000000, true }, + { "uartb", "pll_p", 216000000, false }, + { "uartc", "pll_p", 216000000, false }, { "uartd", "pll_p", 216000000, true }, + { "uarte", "pll_p", 216000000, false }, { "usbd", "clk_m", 12000000, false }, { "usb2", "clk_m", 12000000, false }, { "usb3", "clk_m", 12000000, false }, diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 6497d12..f430351 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -57,6 +57,11 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL), OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL), OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006000, "tegra-uart.0", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006040, "tegra-uart.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006200, "tegra-uart.2", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006300, "tegra-uart.3", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006400, "tegra-uart.4", NULL), OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL), OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL), OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL), @@ -69,6 +74,10 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 408000000, true }, + { "uartb", "pll_p", 408000000, false }, + { "uartc", "pll_p", 408000000, false }, + { "uartd", "pll_p", 408000000, false }, + { "uarte", "pll_p", 408000000, false }, { "pll_a", "pll_p_out1", 564480000, true }, { "pll_a_out0", "pll_a", 11289600, true }, { "extern1", "pll_a_out0", 0, true },