[3/4] ARM: tegra: Add OF_DEV_AUXDATA for uart driver in board dt

Submitted by Laxman Dewangan on Dec. 17, 2012, 12:08 p.m.

Details

Message ID 1355746101-15291-4-git-send-email-ldewangan@nvidia.com
State Superseded, archived
Headers show

Commit Message

Laxman Dewangan Dec. 17, 2012, 12:08 p.m.
Add OF_DEV_AUXDATA for high speed uart controller driver for
Tegra20/Tegra30 board dt files.
Set the parent clock of uart controller to PLLP.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/mach-tegra/board-dt-tegra20.c |    8 ++++++++
 arch/arm/mach-tegra/board-dt-tegra30.c |    9 +++++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

Comments

Stephen Warren Dec. 17, 2012, 9:47 p.m.
On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
> Add OF_DEV_AUXDATA for high speed uart controller driver for
> Tegra20/Tegra30 board dt files.
> Set the parent clock of uart controller to PLLP.

> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c

> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {

> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),

Instead, can we simply get the clocks from device tree? Prashant, how
much effort will that be once your clock patches are checked in, or is
it already part of those patches?

> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>  static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>  	/* name		parent		rate		enabled */
>  	{ "uarta",	"pll_p",	216000000,	true },
> +	{ "uartb",	"pll_p",	216000000,	false },
> +	{ "uartc",	"pll_p",	216000000,	false },
>  	{ "uartd",	"pll_p",	216000000,	true },
> +	{ "uarte",	"pll_p",	216000000,	false },

Prashant's clock patches remove this table. Please work with him to work
out how to deal with that.
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Prashant Gaikwad Dec. 18, 2012, 6:18 a.m.
On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>> Tegra20/Tegra30 board dt files.
>> Set the parent clock of uart controller to PLLP.
>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
> Instead, can we simply get the clocks from device tree? Prashant, how
> much effort will that be once your clock patches are checked in, or is
> it already part of those patches?

It is not part of rework patches, but I will send a patch for it 
immediately after those patches are accepted upstream.

>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>>   static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>>   	/* name		parent		rate		enabled */
>>   	{ "uarta",	"pll_p",	216000000,	true },
>> +	{ "uartb",	"pll_p",	216000000,	false },
>> +	{ "uartc",	"pll_p",	216000000,	false },
>>   	{ "uartd",	"pll_p",	216000000,	true },
>> +	{ "uarte",	"pll_p",	216000000,	false },
> Prashant's clock patches remove this table. Please work with him to work
> out how to deal with that.

Laxman,

If you want I can include these entries in current tables.



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Laxman Dewangan Dec. 18, 2012, 7 a.m.
On Tuesday 18 December 2012 11:48 AM, Prashant Gaikwad wrote:
> On Tuesday 18 December 2012 03:17 AM, Stephen Warren wrote:
>> On 12/17/2012 05:08 AM, Laxman Dewangan wrote:
>>> Add OF_DEV_AUXDATA for high speed uart controller driver for
>>> Tegra20/Tegra30 board dt files.
>>> Set the parent clock of uart controller to PLLP.
>>> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
>>> @@ -94,6 +94,11 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
>>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
>>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
>>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
>>> +	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
>> Instead, can we simply get the clocks from device tree? Prashant, how
>> much effort will that be once your clock patches are checked in, or is
>> it already part of those patches?
> It is not part of rework patches, but I will send a patch for it
> immediately after those patches are accepted upstream.
>
>>> @@ -106,7 +111,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
>>>    static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
>>>    	/* name		parent		rate		enabled */
>>>    	{ "uarta",	"pll_p",	216000000,	true },
>>> +	{ "uartb",	"pll_p",	216000000,	false },
>>> +	{ "uartc",	"pll_p",	216000000,	false },
>>>    	{ "uartd",	"pll_p",	216000000,	true },
>>> +	{ "uarte",	"pll_p",	216000000,	false },
>> Prashant's clock patches remove this table. Please work with him to work
>> out how to deal with that.
> Laxman,
>
> If you want I can include these entries in current tables.

No issue, you can add this in your change.
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Patch hide | download patch | download mbox

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 734d9cc..959c8b3 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -94,6 +94,11 @@  struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006000, "tegra-uart.0", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006040, "tegra-uart.1", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006200, "tegra-uart.2", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006300, "tegra-uart.3", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-hsuart", 0x70006400, "tegra-uart.4", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
@@ -106,7 +111,10 @@  struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	/* name		parent		rate		enabled */
 	{ "uarta",	"pll_p",	216000000,	true },
+	{ "uartb",	"pll_p",	216000000,	false },
+	{ "uartc",	"pll_p",	216000000,	false },
 	{ "uartd",	"pll_p",	216000000,	true },
+	{ "uarte",	"pll_p",	216000000,	false },
 	{ "usbd",	"clk_m",	12000000,	false },
 	{ "usb2",	"clk_m",	12000000,	false },
 	{ "usb3",	"clk_m",	12000000,	false },
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 6497d12..f430351 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -57,6 +57,11 @@  struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006000, "tegra-uart.0", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006040, "tegra-uart.1", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006200, "tegra-uart.2", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006300, "tegra-uart.3", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-hsuart", 0x70006400, "tegra-uart.4", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
@@ -69,6 +74,10 @@  struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	/* name		parent		rate		enabled */
 	{ "uarta",	"pll_p",	408000000,	true },
+	{ "uartb",	"pll_p",	408000000,	false },
+	{ "uartc",	"pll_p",	408000000,	false },
+	{ "uartd",	"pll_p",	408000000,	false },
+	{ "uarte",	"pll_p",	408000000,	false },
 	{ "pll_a",	"pll_p_out1",	564480000,	true },
 	{ "pll_a_out0",	"pll_a",	11289600,	true },
 	{ "extern1",	"pll_a_out0",	0,		true },