From patchwork Mon Dec 17 10:37:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greta Yorsh X-Patchwork-Id: 206813 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 6EB692C0093 for ; Mon, 17 Dec 2012 21:37:48 +1100 (EST) Comment: DKIM? See http://www.dkim.org DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=gcc.gnu.org; s=default; x=1356345469; h=Comment: DomainKey-Signature:Received:Received:Received:Received:Received: From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type: Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:Sender:Delivered-To; bh=q+7E4s98Cwc69VZPRw+G qZvssjs=; b=WORZBYjeqq52wih/i5TVOr+Fvy5Tlp/M5qxLVCnqS7Sb6/9g8LmN eUignN41Q1EF7UR1srtVSxhQQOyGyTWhY0MjB673nT1nap6JIXq6ZK7ip82Bywg+ O+9LV0vPp6xsjStP2gZooMMSs3rImVihTVH697zc5myB5ljHrDXbJgg= Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:From:To:Cc:Subject:Date:Message-ID:MIME-Version:X-MC-Unique:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=PgwSVH+RXhBH0++/ut7Z9NgVQkS1ucSNi5UgynDCsnYD3o22iTsNOt+5TIPahx 17wtjuIvE0kOUiKqsJWFwISKtMlOo9XgNR40z2DHekU2rwWPbzFOMl72XfDAX7RU FR38qTH0+EH9sC+Rpehw0AnoyBTObUjHdHVpSEbWcn5+Y=; Received: (qmail 29445 invoked by alias); 17 Dec 2012 10:37:42 -0000 Received: (qmail 29291 invoked by uid 22791); 17 Dec 2012 10:37:41 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, MSGID_MULTIPLE_AT, RCVD_IN_DNSWL_LOW, TW_QE X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 17 Dec 2012 10:37:08 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 17 Dec 2012 10:37:05 +0000 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 17 Dec 2012 10:37:04 +0000 From: "Greta Yorsh" To: "GCC Patches" Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" , , Subject: [PATCH,ARM] Define simple_alu_shift value for type attribute Date: Mon, 17 Dec 2012 10:37:00 -0000 Message-ID: <000001cddc42$72ba0bc0$582e2340$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 112121710370514601 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The attribute "type" for UXTB, UXTH, SXTB, and SXTH is set to "simple_alu_imm" if tuning is for cortex-a7 and "alu_shift" otherwise (since r193996). The problem is that attributes should not depend on a specific CPU or tuning. To eliminate the dependency, this patch introduces a new value for "type" attribute, called "simple_alu_shift" and updates the relevant insn definitions. This patch also updates all existing pipeline descriptions to use simple_alu_shift in the same way as alu_shift. The motivation for this patch is cortex-a7 pipeline description that will be submitted separately and will handle simple_alu_shift differently from alu_shift. No regression on qemu for arm-none-eabi Cortex-A15. No difference in generated assembly when compiling all of the preprocessed sources of gcc 4.8 as a test in various configurations: -mcpu=cortex-a15 -march=armv6t2 -marm/-mthumb -O0/-O1/-O2/-O3/-Os. Ok for trunk? Thanks, Greta 2012-12-05 Greta Yorsh * config/arm/arm.md (type): Add "simple_alu_shift" to attribute "type". (core_cycles): Update for simple_alu_shift. (thumb1_zero_extendhisi2,arm_zero_extendhisi2_v6): Use simple_alu_shift instead of a CPU-speicific condition for "type" attribute. (thumb1_zero_extendqisi2_v6,arm_zero_extendqisi2_v6): Likewise. (thumb1_extendhisi2,arm_extendhisi2_v6,arm_extendqisi_v6): Likewise. (thumb1_extendqisi2): Likewise. * config/arm/thumb2.md (thumb2_extendqisi_v6): Likewise. (thumb2_zero_extendhisi2_v6,thumb2_zero_extendqisi2_v6) Likewise. * config/arm/arm1020e.md (alu_shift_op): Use simple_alu_shift. * config/arm/arm1026ejs.md (alu_shift_op): Likewise. * config/arm/arm1136jfs.md (11_alu_shift_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu_shift,cortex_a8_mov): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp,cortex_a9_dp_shift): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise. * config/arm/fa526.md (526_alu_shift_op): Likewise. * config/arm/fa606te.md (fa606te_core): Likewise. * config/arm/fa626te.md (626te_alu_shift_op): Likewise. * config/arm/fa726te.md (726te_alu_shift_op): Likewise. * config/arm/fmp626.md (mp626_alu_shift_op): Likewise. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 331203329e7560864597de3caa401c1d1231a24f..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -331,6 +331,7 @@ (define_attr "insn" ; regs or have a shifted source operand ; and does not have an immediate operand. This is ; also the default +; simple_alu_shift covers UXTH, UXTB, SXTH, SXTB ; alu_shift any data instruction that doesn't hit memory or fp ; regs, but has a source operand shifted by a constant ; alu_shift_reg any data instruction that doesn't hit memory or fp @@ -362,6 +363,7 @@ (define_attr "insn" (define_attr "type" "simple_alu_imm,\ alu_reg,\ + simple_alu_shift,\ alu_shift,\ alu_shift_reg,\ mult,\ @@ -543,7 +545,9 @@ (define_attr "write_conflict" "no,yes" ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "simple_alu_imm,alu_reg,alu_shift,float,fdivd,fdivs") + "simple_alu_imm,alu_reg,\ + simple_alu_shift,alu_shift,\ + float,fdivd,fdivs") (const_string "single") (const_string "multi"))) @@ -4712,11 +4716,7 @@ (define_insn "*thumb1_zero_extendhisi2" [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")])] + (set_attr "type" "simple_alu_shift, load_byte")] ) (define_insn "*arm_zero_extendhisi2" @@ -4738,11 +4738,7 @@ (define_insn "*arm_zero_extendhisi2_v6" uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" [(set_attr "predicable" "yes") - (set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")])] + (set_attr "type" "simple_alu_shift,load_byte")] ) (define_insn "*arm_zero_extendhisi2addsi" @@ -4812,11 +4808,7 @@ (define_insn "*thumb1_zero_extendqisi2_v uxtb\\t%0, %1 ldrb\\t%0, %1" [(set_attr "length" "2") - (set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")])] + (set_attr "type" "simple_alu_shift,load_byte")] ) (define_insn "*arm_zero_extendqisi2" @@ -4838,11 +4830,7 @@ (define_insn "*arm_zero_extendqisi2_v6" "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes")] ) @@ -5016,11 +5004,7 @@ (define_insn "thumb1_extendhisi2" [(if_then_else (eq_attr "is_arch6" "yes") (const_int 2) (const_int 4)) (const_int 4)]) - (set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + (set_attr "type" "simple_alu_shift,load_byte") (set_attr "pool_range" "*,1020")] ) @@ -5093,11 +5077,7 @@ (define_insn "*arm_extendhisi2_v6" "@ sxth%?\\t%0, %1 ldr%(sh%)\\t%0, %1" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5197,11 +5177,7 @@ (define_insn "*arm_extendqisi_v6" "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5314,12 +5290,7 @@ (define_insn "thumb1_extendqisi2" (const_int 2) (if_then_else (eq_attr "is_arch6" "yes") (const_int 4) (const_int 6))]) - (set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte") - (const_string "load_byte")])] + (set_attr "type" "simple_alu_shift,load_byte,load_byte")] ) (define_expand "extendsfdf2" diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 3d3ff23e7c64edfb6579a23ecb2cdf31b113cb15..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -72,7 +72,7 @@ (define_insn_reservation "1020alu_op" 1 ;; ALU operations with a shift-by-constant operand (define_insn_reservation "1020alu_shift_op" 1 (and (eq_attr "tune" "arm1020e,arm1022e") - (eq_attr "type" "alu_shift")) + (eq_attr "type" "simple_alu_shift,alu_shift")) "1020a_e,1020a_m,1020a_w") ;; ALU operations with a shift-by-register operand diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index d9ed858f8614de04a80d08e2036873bdb020f84d..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -72,7 +72,7 @@ (define_insn_reservation "alu_op" 1 ;; ALU operations with a shift-by-constant operand (define_insn_reservation "alu_shift_op" 1 (and (eq_attr "tune" "arm1026ejs") - (eq_attr "type" "alu_shift")) + (eq_attr "type" "simple_alu_shift,alu_shift")) "a_e,a_m,a_w") ;; ALU operations with a shift-by-register operand diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index ff5e614b37b6fe2a05ccc8c6f134838cfb3ea74d..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -81,7 +81,7 @@ (define_insn_reservation "11_alu_op" 2 ;; ALU operations with a shift-by-constant operand (define_insn_reservation "11_alu_shift_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") - (eq_attr "type" "alu_shift")) + (eq_attr "type" "simple_alu_shift,alu_shift")) "e_1,e_2,e_3,e_wb") ;; ALU operations with a shift-by-register operand diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index 656a90e41af750134e8521d1b35e7d6b226b2ea8..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -58,7 +58,7 @@ (define_cpu_unit "e,m,w" "arm926ejs") ;; ALU operations with no shifted operand (define_insn_reservation "9_alu_op" 1 (and (eq_attr "tune" "arm926ejs") - (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift")) + (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift")) "e,m,w") ;; ALU operations with a shift-by-register operand diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index f25fcee9f01f024ee3302bc154112347396fc6c2..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -68,7 +68,7 @@ (define_insn_reservation "cortex_a15_alu ;; ALU ops with immediate shift (define_insn_reservation "cortex_a15_alu_shift" 3 (and (eq_attr "tune" "cortexa15") - (and (eq_attr "type" "alu_shift") + (and (eq_attr "type" "simple_alu_shift,alu_shift") (eq_attr "neon_type" "none"))) "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\ |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)") diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 1121c7effcf281e8bb0d9dd8c655864427b3b2ba..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -63,7 +63,7 @@ (define_insn_reservation "cortex_a5_alu" (define_insn_reservation "cortex_a5_alu_shift" 2 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "alu_shift,alu_shift_reg")) + (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) "cortex_a5_ex1") ;; Forwarding path for unshifted operands. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index 7c266d3b71fd35f2bee263429108b6a9442b1913..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -93,7 +93,7 @@ (define_insn_reservation "cortex_a8_alu" (define_insn_reservation "cortex_a8_alu_shift" 2 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "alu_shift") + (and (eq_attr "type" "simple_alu_shift,alu_shift") (not (eq_attr "insn" "mov,mvn")))) "cortex_a8_default") @@ -107,7 +107,7 @@ (define_insn_reservation "cortex_a8_alu_ (define_insn_reservation "cortex_a8_mov" 1 (and (eq_attr "tune" "cortexa8") - (and (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg") + (and (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg") (eq_attr "insn" "mov,mvn"))) "cortex_a8_default") diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 336c4fcefae5ad05f5d31382bece8931b10a848e..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -82,7 +82,7 @@ (define_insn_reservation "cortex_a9_dp" (and (eq_attr "tune" "cortexa9") (ior (and (eq_attr "type" "alu_reg,simple_alu_imm") (eq_attr "neon_type" "none")) - (and (and (eq_attr "type" "alu_shift_reg, alu_shift") + (and (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") (eq_attr "insn" "mov")) (eq_attr "neon_type" "none")))) "cortex_a9_p0_default|cortex_a9_p1_default") @@ -90,7 +90,7 @@ (define_insn_reservation "cortex_a9_dp" ;; An instruction using the shifter will go down E1. (define_insn_reservation "cortex_a9_dp_shift" 3 (and (eq_attr "tune" "cortexa9") - (and (eq_attr "type" "alu_shift_reg, alu_shift") + (and (eq_attr "type" "alu_shift_reg, simple_alu_shift,alu_shift") (not (eq_attr "insn" "mov")))) "cortex_a9_p0_shift | cortex_a9_p1_shift") diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index bff17dd77fba06384363b2d9f8796deb81c4f76e..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -31,7 +31,7 @@ (define_reservation "cortex_m4_ex" "cort ;; ALU and multiply is one cycle. (define_insn_reservation "cortex_m4_alu" 1 (and (eq_attr "tune" "cortexm4") - (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg,mult")) + (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg,mult")) "cortex_m4_ex") ;; Byte, half-word and word load is two cycles. diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index 26de65aa1b3d89c949b24d203e93d1497ed1593f..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -90,7 +90,7 @@ (define_insn_reservation "cortex_r4_mov" (define_insn_reservation "cortex_r4_alu_shift" 2 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "alu_shift")) + (eq_attr "type" "simple_alu_shift,alu_shift")) "cortex_r4_alu") (define_insn_reservation "cortex_r4_alu_shift_reg" 2 diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index 2b89bb5429b41e9183bc55949f2a54bf55fec7fd..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -67,7 +67,7 @@ (define_insn_reservation "526_alu_op" 1 (define_insn_reservation "526_alu_shift_op" 2 (and (eq_attr "tune" "fa526") - (eq_attr "type" "alu_shift,alu_shift_reg")) + (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) "fa526_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 4725b93b6cc5bf13d375103e8769db05591661e2..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -62,7 +62,7 @@ (define_cpu_unit "fa606te_core" "fa606te ;; ALU operations (define_insn_reservation "606te_alu_op" 1 (and (eq_attr "tune" "fa606te") - (eq_attr "type" "alu_reg,simple_alu_imm,alu_shift,alu_shift_reg")) + (eq_attr "type" "alu_reg,simple_alu_imm,simple_alu_shift,alu_shift,alu_shift_reg")) "fa606te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index bed3995a5e2548cf63f1055c3d0d7c757c479b5d..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -73,7 +73,7 @@ (define_insn_reservation "626te_alu_op" (define_insn_reservation "626te_alu_shift_op" 2 (and (eq_attr "tune" "fa626,fa626te") - (eq_attr "type" "alu_shift,alu_shift_reg")) + (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) "fa626te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index a4c256ce22e7f9fdf33cdf81821ca6588c8583b3..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -95,7 +95,7 @@ (define_insn_reservation "726te_alu_op" ;; it takes 3 cycles. (define_insn_reservation "726te_alu_shift_op" 3 (and (eq_attr "tune" "fa726te") - (and (eq_attr "type" "alu_shift") + (and (eq_attr "type" "simple_alu_shift,alu_shift") (not (eq_attr "insn" "mov,mvn")))) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 228817c85e5c5fa07b7a9c83d752005017eb8da4..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -68,7 +68,7 @@ (define_insn_reservation "mp626_alu_op" (define_insn_reservation "mp626_alu_shift_op" 2 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu_shift,alu_shift_reg")) + (eq_attr "type" "simple_alu_shift,alu_shift,alu_shift_reg")) "fmp626_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 19158a294191e73034b3490328202980af7bd498..0000000000000000000000000000000000000000 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -568,11 +568,7 @@ (define_insn "*thumb2_extendqisi_v6" "@ sxtb%?\\t%0, %1 ldr%(sb%)\\t%0, %1" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")] @@ -585,11 +581,7 @@ (define_insn "*thumb2_zero_extendhisi2_v "@ uxth%?\\t%0, %1 ldr%(h%)\\t%0, %1" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")] @@ -602,11 +594,7 @@ (define_insn "thumb2_zero_extendqisi2_v6 "@ uxtb%(%)\\t%0, %1 ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr_alternative "type" - [(if_then_else (eq_attr "tune" "cortexa7") - (const_string "simple_alu_imm") - (const_string "alu_shift")) - (const_string "load_byte")]) + [(set_attr "type" "simple_alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") (set_attr "neg_pool_range" "*,250")]