From patchwork Fri Dec 14 12:13:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 206480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C2C882C008C for ; Sat, 15 Dec 2012 00:51:18 +1100 (EST) Received: from localhost ([::1]:54196 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUBP-0007T6-6D for incoming@patchwork.ozlabs.org; Fri, 14 Dec 2012 07:16:03 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56424) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUAC-0005Qn-TV for qemu-devel@nongnu.org; Fri, 14 Dec 2012 07:15:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TjUA6-0000xp-Pe for qemu-devel@nongnu.org; Fri, 14 Dec 2012 07:14:48 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39291 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUA6-0000xI-G5; Fri, 14 Dec 2012 07:14:42 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 56BFEA51F2; Fri, 14 Dec 2012 13:14:08 +0100 (CET) From: Alexander Graf To: "qemu-ppc@nongnu.org List" Date: Fri, 14 Dec 2012 13:13:33 +0100 Message-Id: <1355487236-27451-18-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1355487236-27451-1-git-send-email-agraf@suse.de> References: <1355487236-27451-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-devel qemu-devel Subject: [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical, just that the MPIC one can also raise critical interrupts. Combine those two and check for critical raise capability during runtime. Signed-off-by: Alexander Graf --- hw/openpic.c | 34 ++++++++++++++++------------------ hw/openpic.h | 3 +++ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 2a3b56a..d709e36 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -207,6 +207,9 @@ typedef struct openpic_t { PCIDevice pci_dev; MemoryRegion mem; + /* Behavior control */ + uint32_t flags; + /* Sub-regions */ MemoryRegion sub_io_mem[7]; @@ -234,9 +237,10 @@ typedef struct openpic_t { int irq_ipi0; int irq_tim0; void (*reset) (void *); - void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); } openpic_t; +static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src); + static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) { set_bit(q->queue, n_IRQ); @@ -321,7 +325,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) return; } DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ); - opp->irq_raise(opp, n_CPU, src); + openpic_irq_raise(opp, n_CPU, src); } /* update pic state because registers for n_IRQ have changed value */ @@ -753,7 +757,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", idx, n_IRQ); - opp->irq_raise(opp, idx, src); + openpic_irq_raise(opp, idx, src); } break; default: @@ -996,7 +1000,13 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id) static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) { - qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); + int n_ci = IDR_CI0 - n_CPU; + + if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && test_bit(&src->ide, n_ci)) { + qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); + } else { + qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); + } } qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, @@ -1059,7 +1069,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, openpic_save, openpic_load, opp); qemu_register_reset(openpic_reset, opp); - opp->irq_raise = openpic_irq_raise; opp->reset = openpic_reset; if (pmem) @@ -1068,18 +1077,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); } -static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) -{ - int n_ci = IDR_CI0 - n_CPU; - - if(test_bit(&src->ide, n_ci)) { - qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); - } - else { - qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); - } -} - static void mpic_reset (void *opaque) { openpic_t *mpp = (openpic_t *)opaque; @@ -1265,7 +1262,8 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base, mpp->dst[i].irqs = irqs[i]; mpp->irq_out = irq_out; - mpp->irq_raise = mpic_irq_raise; + /* Enable critical interrupt support */ + mpp->flags |= OPENPIC_FLAG_IDE_CRIT; mpp->reset = mpic_reset; register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp); diff --git a/hw/openpic.h b/hw/openpic.h index f50a1e4..1232d10 100644 --- a/hw/openpic.h +++ b/hw/openpic.h @@ -11,6 +11,9 @@ enum { OPENPIC_OUTPUT_NB, }; +/* OpenPIC capability flags */ +#define OPENPIC_FLAG_IDE_CRIT (1 << 0) + qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, qemu_irq **irqs, qemu_irq irq_out); qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,