From patchwork Fri Dec 14 12:13:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 206434 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 97EAD2C0040 for ; Fri, 14 Dec 2012 23:42:08 +1100 (EST) Received: from localhost ([::1]:52463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUAl-0006Pz-Mr for incoming@patchwork.ozlabs.org; Fri, 14 Dec 2012 07:15:23 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUAC-0005PG-Bt for qemu-devel@nongnu.org; Fri, 14 Dec 2012 07:15:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TjUA6-0000y4-Ru for qemu-devel@nongnu.org; Fri, 14 Dec 2012 07:14:48 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39288 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TjUA6-0000xB-FR; Fri, 14 Dec 2012 07:14:42 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 62CCFA51CA; Fri, 14 Dec 2012 13:14:07 +0100 (CET) From: Alexander Graf To: "qemu-ppc@nongnu.org List" Date: Fri, 14 Dec 2012 13:13:30 +0100 Message-Id: <1355487236-27451-15-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1355487236-27451-1-git-send-email-agraf@suse.de> References: <1355487236-27451-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-devel qemu-devel Subject: [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The openpic code was still using the old mmio memory api. Convert it to be a generic memory api user and clean up some code that becomes redundant that way. Signed-off-by: Alexander Graf --- hw/openpic.c | 138 ++++++++++++++++++++-------------------------------------- 1 files changed, 48 insertions(+), 90 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 122ce76..1d714f4 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -461,7 +461,8 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val) opp->src[n_IRQ].ipvp); } -static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val) +static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_t *opp = opaque; IRQ_dst_t *dst; @@ -527,7 +528,7 @@ static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val) } } -static uint32_t openpic_gbl_read (void *opaque, hwaddr addr) +static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) { openpic_t *opp = opaque; uint32_t retval; @@ -584,7 +585,8 @@ static uint32_t openpic_gbl_read (void *opaque, hwaddr addr) return retval; } -static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) +static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_t *opp = opaque; int idx; @@ -615,7 +617,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) } } -static uint32_t openpic_timer_read (void *opaque, uint32_t addr) +static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len) { openpic_t *opp = opaque; uint32_t retval; @@ -648,7 +650,8 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr) return retval; } -static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) +static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_t *opp = opaque; int idx; @@ -667,7 +670,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) } } -static uint32_t openpic_src_read (void *opaque, uint32_t addr) +static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) { openpic_t *opp = opaque; uint32_t retval; @@ -749,7 +752,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, } } -static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val) +static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); } @@ -833,96 +837,63 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, return retval; } -static uint32_t openpic_cpu_read(void *opaque, hwaddr addr) +static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) { return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); } -static void openpic_buggy_write (void *opaque, - hwaddr addr, uint32_t val) -{ - printf("Invalid OPENPIC write access !\n"); -} - -static uint32_t openpic_buggy_read (void *opaque, hwaddr addr) -{ - printf("Invalid OPENPIC read access !\n"); - - return -1; -} - -static void openpic_writel (void *opaque, - hwaddr addr, uint32_t val) +static void openpic_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_t *opp = opaque; - addr &= 0x3FFFF; DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); if (addr < 0x1100) { /* Global registers */ - openpic_gbl_write(opp, addr, val); + openpic_gbl_write(opp, addr, val, len); } else if (addr < 0x10000) { /* Timers registers */ - openpic_timer_write(opp, addr, val); + openpic_timer_write(opp, addr, val, len); } else if (addr < 0x20000) { /* Source registers */ - openpic_src_write(opp, addr, val); + openpic_src_write(opp, addr, val, len); } else { /* CPU registers */ - openpic_cpu_write(opp, addr, val); + openpic_cpu_write(opp, addr, val, len); } } -static uint32_t openpic_readl (void *opaque,hwaddr addr) +static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len) { openpic_t *opp = opaque; uint32_t retval; - addr &= 0x3FFFF; DPRINTF("%s: offset %08x\n", __func__, (int)addr); if (addr < 0x1100) { /* Global registers */ - retval = openpic_gbl_read(opp, addr); + retval = openpic_gbl_read(opp, addr, len); } else if (addr < 0x10000) { /* Timers registers */ - retval = openpic_timer_read(opp, addr); + retval = openpic_timer_read(opp, addr, len); } else if (addr < 0x20000) { /* Source registers */ - retval = openpic_src_read(opp, addr); + retval = openpic_src_read(opp, addr, len); } else { /* CPU registers */ - retval = openpic_cpu_read(opp, addr); + retval = openpic_cpu_read(opp, addr, len); } return retval; } -static uint64_t openpic_read(void *opaque, hwaddr addr, - unsigned size) -{ - openpic_t *opp = opaque; - - switch (size) { - case 4: return openpic_readl(opp, addr); - default: return openpic_buggy_read(opp, addr); - } -} - -static void openpic_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) -{ - openpic_t *opp = opaque; - - switch (size) { - case 4: return openpic_writel(opp, addr, data); - default: return openpic_buggy_write(opp, addr, data); - } -} - static const MemoryRegionOps openpic_ops = { .read = openpic_read, .write = openpic_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) @@ -1131,7 +1102,8 @@ static void mpic_reset (void *opaque) mpp->glbc = 0x00000000; } -static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val) +static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val, + unsigned len) { openpic_t *mpp = opaque; int idx, cpu; @@ -1139,7 +1111,6 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val) DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); if (addr & 0xF) return; - addr &= 0xFFFF; cpu = addr >> 12; idx = (addr >> 6) & 0x3; switch (addr & 0x30) { @@ -1164,7 +1135,7 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val) } } -static uint32_t mpic_timer_read (void *opaque, hwaddr addr) +static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len) { openpic_t *mpp = opaque; uint32_t retval; @@ -1174,7 +1145,6 @@ static uint32_t mpic_timer_read (void *opaque, hwaddr addr) retval = 0xFFFFFFFF; if (addr & 0xF) return retval; - addr &= 0xFFFF; cpu = addr >> 12; idx = (addr >> 6) & 0x3; switch (addr & 0x30) { @@ -1242,45 +1212,33 @@ static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len) } static const MemoryRegionOps mpic_glb_ops = { - .old_mmio = { - .write = { openpic_buggy_write, - openpic_buggy_write, - openpic_gbl_write, - }, - .read = { openpic_buggy_read, - openpic_buggy_read, - openpic_gbl_read, - }, - }, + .write = openpic_gbl_write, + .read = openpic_gbl_read, .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static const MemoryRegionOps mpic_tmr_ops = { - .old_mmio = { - .write = { openpic_buggy_write, - openpic_buggy_write, - mpic_timer_write, - }, - .read = { openpic_buggy_read, - openpic_buggy_read, - mpic_timer_read, - }, - }, + .write = mpic_timer_write, + .read = mpic_timer_read, .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static const MemoryRegionOps mpic_cpu_ops = { - .old_mmio = { - .write = { openpic_buggy_write, - openpic_buggy_write, - openpic_cpu_write, - }, - .read = { openpic_buggy_read, - openpic_buggy_read, - openpic_cpu_read, - }, - }, + .write = openpic_cpu_write, + .read = openpic_cpu_read, .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static const MemoryRegionOps mpic_irq_ops = {