From patchwork Fri Dec 14 02:12:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [5/6] openpic: BRR1 is not a CPU-specific register. From: Scott Wood X-Patchwork-Id: 206273 Message-Id: <1355451124-2559-6-git-send-email-scottwood@freescale.com> To: Alexander Graf Cc: Scott Wood , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Date: Thu, 13 Dec 2012 20:12:03 -0600 It's in the address range that normally contains a magic redirection to the CPU-specific region of the curretn CPU, but it isn't actually a per-CPU register. On real hardware BRR1 shows up only at 0x40000, not at 0x60000 or other non-magic per-CPU areas. Plus, this makes it possible to read the register on the QEMU command line with "xp". Signed-off-by: Scott Wood --- hw/openpic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index c57a168..c0c4307 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -580,6 +580,8 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) retval = 0x00000000; break; case 0x00: /* Block Revision Register1 (BRR1) */ + retval = opp->brr1; + break; case 0x40: case 0x50: case 0x60: @@ -881,9 +883,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, dst = &opp->dst[idx]; addr &= 0xFF0; switch (addr) { - case 0x00: /* Block Revision Register1 (BRR1) */ - retval = opp->brr1; - break; case 0x80: /* PCTP */ retval = dst->pctp; break;