Patchwork [5/6] openpic: BRR1 is not a CPU-specific register.

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Submitter Scott Wood
Date Dec. 14, 2012, 2:12 a.m.
Message ID <1355451124-2559-6-git-send-email-scottwood@freescale.com>
Download mbox | patch
Permalink /patch/206273/
State New
Headers show

Comments

Scott Wood - Dec. 14, 2012, 2:12 a.m.
It's in the address range that normally contains a magic redirection
to the CPU-specific region of the curretn CPU, but it isn't actually
a per-CPU register.  On real hardware BRR1 shows up only at 0x40000,
not at 0x60000 or other non-magic per-CPU areas.  Plus, this makes
it possible to read the register on the QEMU command line with "xp".

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 hw/openpic.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Patch

diff --git a/hw/openpic.c b/hw/openpic.c
index c57a168..c0c4307 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -580,6 +580,8 @@  static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
         retval = 0x00000000;
         break;
     case 0x00: /* Block Revision Register1 (BRR1) */
+        retval = opp->brr1;
+        break;
     case 0x40:
     case 0x50:
     case 0x60:
@@ -881,9 +883,6 @@  static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
-    case 0x00: /* Block Revision Register1 (BRR1) */
-        retval = opp->brr1;
-        break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
         break;