From patchwork Wed Dec 12 18:43:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Kleen X-Patchwork-Id: 205607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 1ADAC2C0095 for ; Thu, 13 Dec 2012 05:43:39 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:X-ExtLoop1:Received:Received:From:To:Cc:Subject:References:Date:In-Reply-To:Message-ID:User-Agent:MIME-Version:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=X/pExWWx6+SCM3hQZAKk/7aYhZfyph+SsIa22iPjc31j3bK7fyO1coRLm+WpzA rKEa5FBoRUeaxdBVUOtMvilt1apbHA1Etq46p74jJZGxmjEguJ3ApccXEnCHL2sR W1qh/nFYqw+e7ZwUTru+Qy2QxzMrZahEo/0W7CcIJNW/c=; Received: (qmail 30550 invoked by alias); 12 Dec 2012 18:43:31 -0000 Received: (qmail 30532 invoked by uid 22791); 12 Dec 2012 18:43:29 -0000 X-SWARE-Spam-Status: No, hits=-6.4 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, RCVD_IN_DNSWL_HI, RCVD_IN_HOSTKARMA_W, TW_AV X-Spam-Check-By: sourceware.org Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 12 Dec 2012 18:43:22 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 12 Dec 2012 10:43:21 -0800 X-ExtLoop1: 1 Received: from tassilo.jf.intel.com ([10.7.201.84]) by fmsmga001.fm.intel.com with ESMTP; 12 Dec 2012 10:43:05 -0800 Received: by tassilo.jf.intel.com (Postfix, from userid 501) id C343D2438FD; Wed, 12 Dec 2012 10:43:05 -0800 (PST) From: Andi Kleen To: Jan Hubicka Cc: Xinliang David Li , GCC Patches , Teresa Johnson Subject: Re: [PATCH i386]: Enable push/pop in pro/epilogue for modern CPUs References: <20121212163722.GA21037@atrey.karlin.mff.cuni.cz> <20121212183036.GB5303@atrey.karlin.mff.cuni.cz> Date: Wed, 12 Dec 2012 10:43:05 -0800 In-Reply-To: (Andi Kleen's message of "Wed, 12 Dec 2012 10:37:36 -0800") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Andi Kleen writes: > >>> > /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more >>> > than 4 branch instructions in the 16 byte window. */ >>> > - m_PPRO | m_P4_NOCONA | m_CORE2I7 | m_ATOM | m_AMD_MULTIPLE | m_GENERIC, >>> > + m_PPRO | m_P4_NOCONA | m_ATOM | m_AMD_MULTIPLE | m_GENERIC, >> >> This is special passs to handle limitations of AMD's K7/K8/K10 branch prediction. >> Intel never had similar design, so this flag is pointless. > > Actually the Sandy Bridge decoded icache has a limit of 3 jumps per > 16 byte window. Actually it's four per 32bytes, sorry. Here's an old patch I had lying around to optimize for that. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 1b871be..9b57316 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2713,6 +2713,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD}, { "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE}, { "-mprefer-avx128", MASK_PREFER_AVX128}, + { "-mjump-pad-32bytes", MASK_JUMP_PAD_32BYTES}, }; const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2]; @@ -32182,6 +32183,7 @@ ix86_avoid_jump_mispredicts (void) rtx insn, start = get_insns (); int nbytes = 0, njumps = 0; int isjump = 0; + int jump_pad_window_size = TARGET_JUMP_PAD_32BYTES ? 32 : 16; /* Look for all minimal intervals of instructions containing 4 jumps. The intervals are bounded by START and INSN. NBYTES is the total @@ -32202,8 +32204,8 @@ ix86_avoid_jump_mispredicts (void) int align = label_to_alignment (insn); int max_skip = label_to_max_skip (insn); - if (max_skip > 15) - max_skip = 15; + if (max_skip > jump_pad_window_size - 1) + max_skip = jump_pad_window_size - 1; /* If align > 3, only up to 16 - max_skip - 1 bytes can be already in the current 16 byte page, because otherwise ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer @@ -32216,7 +32218,7 @@ ix86_avoid_jump_mispredicts (void) INSN_UID (insn), max_skip); if (max_skip) { - while (nbytes + max_skip >= 16) + while (nbytes + max_skip >= jump_pad_window_size) { start = NEXT_INSN (start); if ((JUMP_P (start) @@ -32262,10 +32264,11 @@ ix86_avoid_jump_mispredicts (void) fprintf (dump_file, "Interval %i to %i has %i bytes\n", INSN_UID (start), INSN_UID (insn), nbytes); - if (njumps == 3 && isjump && nbytes < 16) + if (njumps == 3 && isjump && nbytes < jump_pad_window_size) { - int padsize = 15 - nbytes + min_insn_size (insn); - + int padsize = jump_pad_window_size - 1 - nbytes + + min_insn_size (insn); + if (dump_file) fprintf (dump_file, "Padding insn %i by %i bytes!\n", INSN_UID (insn), padsize); diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 6c516e7..b38d163 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -223,6 +223,10 @@ mintel-syntax Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) ;; Deprecated +mjump-pad-32bytes +Target RejectNegative Mask(JUMP_PAD_32BYTES) Save +Avoid more than 4 jumps in each 32byte code window. + mms-bitfields Target Report Mask(MS_BITFIELD_LAYOUT) Save Use native (MS) bitfield layout