From patchwork Wed Dec 12 14:12:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 205553 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E4B002C0097 for ; Thu, 13 Dec 2012 01:48:09 +1100 (EST) Received: from localhost ([::1]:34711 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tin3W-0000Ay-OG for incoming@patchwork.ozlabs.org; Wed, 12 Dec 2012 09:13:02 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tin33-0008Cm-Qp for qemu-devel@nongnu.org; Wed, 12 Dec 2012 09:12:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tin2t-0001xt-QM for qemu-devel@nongnu.org; Wed, 12 Dec 2012 09:12:33 -0500 Received: from cantor2.suse.de ([195.135.220.15]:37562 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tin2t-0001xf-GZ; Wed, 12 Dec 2012 09:12:23 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 18673A50E4; Wed, 12 Dec 2012 15:12:23 +0100 (CET) From: Alexander Graf To: "qemu-ppc@nongnu.org List" Date: Wed, 12 Dec 2012 15:12:05 +0100 Message-Id: <1355321539-23685-6-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1355321539-23685-1-git-send-email-agraf@suse.de> References: <1355321539-23685-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-devel qemu-devel Subject: [Qemu-devel] [PATCH 05/19] openpic: Convert subregions to memory api X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The "openpic" controller is currently using one big region and does subregion dispatching manually. Move this to the memory api. Signed-off-by: Alexander Graf --- hw/openpic.c | 106 +++++++++++++++++++++++++++++++++------------------------ 1 files changed, 61 insertions(+), 45 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index b671d9d..2a3b56a 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -79,6 +79,15 @@ enum { #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */ #endif +#define OPENPIC_GLB_REG_START 0x0 +#define OPENPIC_GLB_REG_SIZE 0x10F0 +#define OPENPIC_TMR_REG_START 0x10F0 +#define OPENPIC_TMR_REG_SIZE 0x220 +#define OPENPIC_SRC_REG_START 0x10000 +#define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20) +#define OPENPIC_CPU_REG_START 0x20000 +#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) + /* MPIC */ #define MPIC_MAX_CPU 1 #define MPIC_MAX_EXT 12 @@ -842,53 +851,39 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); } -static void openpic_write(void *opaque, hwaddr addr, uint64_t val, - unsigned len) -{ - openpic_t *opp = opaque; - - DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); - if (addr < 0x1100) { - /* Global registers */ - openpic_gbl_write(opp, addr, val, len); - } else if (addr < 0x10000) { - /* Timers registers */ - openpic_timer_write(opp, addr, val, len); - } else if (addr < 0x20000) { - /* Source registers */ - openpic_src_write(opp, addr, val, len); - } else { - /* CPU registers */ - openpic_cpu_write(opp, addr, val, len); - } -} - -static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len) -{ - openpic_t *opp = opaque; - uint32_t retval; +static const MemoryRegionOps openpic_glb_ops = { + .write = openpic_gbl_write, + .read = openpic_gbl_read, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; - DPRINTF("%s: offset %08x\n", __func__, (int)addr); - if (addr < 0x1100) { - /* Global registers */ - retval = openpic_gbl_read(opp, addr, len); - } else if (addr < 0x10000) { - /* Timers registers */ - retval = openpic_timer_read(opp, addr, len); - } else if (addr < 0x20000) { - /* Source registers */ - retval = openpic_src_read(opp, addr, len); - } else { - /* CPU registers */ - retval = openpic_cpu_read(opp, addr, len); - } +static const MemoryRegionOps openpic_tmr_ops = { + .write = openpic_timer_write, + .read = openpic_timer_read, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; - return retval; -} +static const MemoryRegionOps openpic_cpu_ops = { + .write = openpic_cpu_write, + .read = openpic_cpu_read, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; -static const MemoryRegionOps openpic_ops = { - .read = openpic_read, - .write = openpic_write, +static const MemoryRegionOps openpic_src_ops = { + .write = openpic_src_write, + .read = openpic_src_read, .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 4, @@ -1009,12 +1004,33 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, { openpic_t *opp; int i, m; + struct { + const char *name; + MemoryRegionOps const *ops; + hwaddr start_addr; + ram_addr_t size; + } const list[] = { + {"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, + {"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, + {"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, + {"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, + }; /* XXX: for now, only one CPU is supported */ if (nb_cpus != 1) return NULL; opp = g_malloc0(sizeof(openpic_t)); - memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000); + + memory_region_init(&opp->mem, "openpic", 0x40000); + + for (i = 0; i < ARRAY_SIZE(list); i++) { + + memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp, + list[i].name, list[i].size); + + memory_region_add_subregion(&opp->mem, list[i].start_addr, + &opp->sub_io_mem[i]); + } // isu_base &= 0xFFFC0000; opp->nb_cpus = nb_cpus;