From patchwork Tue Dec 11 16:06:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Vincent_Stehl=C3=A9?= X-Patchwork-Id: 205267 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 95FCC2C0086 for ; Wed, 12 Dec 2012 03:07:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D57B84A146; Tue, 11 Dec 2012 17:07:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WPEeIpEdan6z; Tue, 11 Dec 2012 17:07:00 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0990B4A14C; Tue, 11 Dec 2012 17:06:59 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 209E44A138 for ; Tue, 11 Dec 2012 17:06:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yc-F+-t9TRDe for ; Tue, 11 Dec 2012 17:06:56 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id B5FA64A13C for ; Tue, 11 Dec 2012 17:06:54 +0100 (CET) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qBBG6oWR008331; Tue, 11 Dec 2012 10:06:50 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBBG6oFx024595; Tue, 11 Dec 2012 10:06:50 -0600 Received: from dlelxv23.itg.ti.com (172.17.1.198) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Tue, 11 Dec 2012 10:06:49 -0600 Received: from svrhermes.tif.ti.com (svrhermes.tif.ti.com [137.167.130.169]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBBG6nBE030640; Tue, 11 Dec 2012 10:06:49 -0600 Received: from unb0919505.tif.ti.com (unb0919505.tif.ti.com [137.167.100.142]) by svrhermes.tif.ti.com (Postfix) with ESMTP id 1BA4437011; Tue, 11 Dec 2012 17:06:49 +0100 (MET) Received: from vstehle by unb0919505.tif.ti.com with local (Exim 4.76) (envelope-from ) id 1TiSM4-0003bx-JF; Tue, 11 Dec 2012 17:06:48 +0100 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= To: Date: Tue, 11 Dec 2012 17:06:20 +0100 Message-ID: <1355241981-13752-2-git-send-email-v-stehle@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355241981-13752-1-git-send-email-v-stehle@ti.com> References: <50C7549D.5080907@ti.com> <1355241981-13752-1-git-send-email-v-stehle@ti.com> MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH v3 1/2] ARM: cache: introduce weak arm_setup_identity_mapping X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Separate the MMU identity mapping for ARM in a weak function, to allow redefinition with platform specific function. This is motivated by the need to unmap the region near address zero on HS OMAP devices, to avoid speculative accesses. Accessing this region causes security violations, which we want to avoid. Signed-off-by: Vincent Stehlé Cc: Tom Rini --- Changes for v3: - Add definition of __arm_setup_identity_mapping() into asm/cache.h - Fix comments style arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 22 +++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..328377b 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void __arm_setup_identity_mapping(u32 *page_table); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 939de10..f785ff5 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@ #include #include +#include +#include #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -40,6 +42,17 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu"))); +void __arm_setup_identity_mapping(u32 *page_table) +{ + int i; + + /* Set up an identity-mapping for all 4GB, rw for everyone */ + for (i = 0; i < 4096; i++) + page_table[i] = i << 20 | (3 << 10) | 0x12; +} +__weak void arm_setup_identity_mapping(u32 *page_table) + __attribute__((alias("__arm_setup_identity_mapping"))); + static void cp_delay (void) { volatile int i; @@ -72,9 +85,12 @@ static inline void mmu_setup(void) u32 reg; arm_init_before_mmu(); - /* Set up an identity-mapping for all 4GB, rw for everyone */ - for (i = 0; i < 4096; i++) - page_table[i] = i << 20 | (3 << 10) | 0x12; + + /* + * Set up an identity-mapping. Default version maps all 4GB rw for + * everyone + */ + arm_setup_identity_mapping(page_table); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { dram_bank_mmu_setup(i);