Patchwork [2/3] Make-repl_ph-to-sign-extended-to-target_long

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Submitter Jovanovic, Petar
Date Dec. 11, 2012, 3:06 p.m.
Message ID <874D219413C17C42B1D2E0432B92BE5CBBE2911A@exchdb03.mips.com>
Download mbox | patch
Permalink /patch/205253/
State New
Headers show

Comments

Jovanovic, Petar - Dec. 11, 2012, 3:06 p.m.
lgtm, though I wish there was a test for this in repl_ph.c.

+ cc Aurelien J.

Petar
Aurelien Jarno - Jan. 1, 2013, 10:59 a.m.
On Tue, Dec 11, 2012 at 03:06:35PM +0000, Jovanovic, Petar wrote:
> lgtm, though I wish there was a test for this in repl_ph.c.
> 
> + cc Aurelien J.
> 
> Petar
> ________________________________________
> From: Dongxue Zhang [elta.era@gmail.com]
> Sent: Tuesday, December 11, 2012 3:28 PM
> To: qemu-devel@nongnu.org
> Cc: chenwj@iis.sinica.edu.tw; Jovanovic, Petar; rth@twiddle.net; Dongxue Zhang
> Subject: [PATCH 2/3] Make-repl_ph-to-sign-extended-to-target_long
> 
> The immediate value is 9bits, should sign-extend to 16bits. The return value to
> register should sign-extend to target_long, as Richard says, removing an
> unnecessary cast works fun.
> 
> Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
> ---
>  target-mips/translate.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 65e6725..1701ca3 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -13769,9 +13769,10 @@ static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
>              check_dsp(ctx);
>              {
>                  imm = (ctx->opcode >> 16) & 0x03FF;
> +                imm = (int16_t)(imm << 6) >> 6;
>                  tcg_gen_movi_tl(cpu_gpr[ret], \
>                                  (target_long)((int32_t)imm << 16 | \
> -                                (uint32_t)(uint16_t)imm));
> +                                (uint16_t)imm));
>              }
>              break;
>          case OPC_REPLV_PH:

Thanks, I have applied the patch after fixing the subject.

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 65e6725..1701ca3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13769,9 +13769,10 @@  static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
             check_dsp(ctx);
             {
                 imm = (ctx->opcode >> 16) & 0x03FF;
+                imm = (int16_t)(imm << 6) >> 6;
                 tcg_gen_movi_tl(cpu_gpr[ret], \
                                 (target_long)((int32_t)imm << 16 | \
-                                (uint32_t)(uint16_t)imm));
+                                (uint16_t)imm));
             }
             break;
         case OPC_REPLV_PH: