Patchwork [2/3] Make-repl_ph-to-sign-extended-to-target_long

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Submitter Dongxue Zhang
Date Dec. 11, 2012, 2:28 p.m.
Message ID <1355236110-4159-2-git-send-email-elta.era@gmail.com>
Download mbox | patch
Permalink /patch/205247/
State New
Headers show

Comments

Dongxue Zhang - Dec. 11, 2012, 2:28 p.m.
The immediate value is 9bits, should sign-extend to 16bits. The return value to
register should sign-extend to target_long, as Richard says, removing an
unnecessary cast works fun.

Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
---
 target-mips/translate.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
Markus Armbruster - Dec. 11, 2012, 3:13 p.m.
Please-separate-words-with-spaces-in-your-subject-line-thank-you-:)
Andreas Färber - Dec. 11, 2012, 6:39 p.m.
Am 11.12.2012 16:13, schrieb Markus Armbruster:
> Please-separate-words-with-spaces-in-your-subject-line-thank-you-:)

Also all three patches should have a "target-mips: " prefix in the
subject to make clear what they touch and who must review and later
commit these.

Andreas
Dongxue Zhang - Dec. 12, 2012, 6:43 a.m.
Thanks for your review, now I know this problem but don't have gcc can
compile repl_ph instruction. I will build a gcc and resend this patch later.


2012/12/12 Andreas Färber <afaerber@suse.de>

> Am 11.12.2012 16:13, schrieb Markus Armbruster:
> > Please-separate-words-with-spaces-in-your-subject-line-thank-you-:)
>
> Also all three patches should have a "target-mips: " prefix in the
> subject to make clear what they touch and who must review and later
> commit these.
>
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
>

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 65e6725..1701ca3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13769,9 +13769,10 @@  static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
             check_dsp(ctx);
             {
                 imm = (ctx->opcode >> 16) & 0x03FF;
+                imm = (int16_t)(imm << 6) >> 6;
                 tcg_gen_movi_tl(cpu_gpr[ret], \
                                 (target_long)((int32_t)imm << 16 | \
-                                (uint32_t)(uint16_t)imm));
+                                (uint16_t)imm));
             }
             break;
         case OPC_REPLV_PH: