From patchwork Tue Dec 11 11:01:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,1/5] EXYNOS5: Change parent clock of FIMD to MPLL Date: Tue, 11 Dec 2012 01:01:22 -0000 From: Ajay Kumar X-Patchwork-Id: 205177 Message-Id: <1355223686-13718-1-git-send-email-ajaykumar.rs@samsung.com> To: u-boot@lists.denx.de Cc: inki.dae@samsung.com, dh09.lee@samsung.com With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to resolves this issue. Signed-off-by: Ajay Kumar Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..bfcd5f7 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void) */ cfg = readl(&clk->src_disp1_0); cfg &= ~(0xf); - cfg |= 0x8; + cfg |= 0x6; writel(cfg, &clk->src_disp1_0); /*