| Submitter | Ajay Kumar |
|---|---|
| Date | Dec. 11, 2012, 11:01 a.m. |
| Message ID | <1355223686-13718-1-git-send-email-ajaykumar.rs@samsung.com> |
| Download | mbox | patch |
| Permalink | /patch/205177/ |
| State | Changes Requested |
| Delegated to: | Minkyu Kang |
| Headers | show |
Comments
Hi Ajay, On Tue, Dec 11, 2012 at 3:01 AM, Ajay Kumar <ajaykumar.rs@samsung.com> wrote: > With VPLL as source clock to FIMD, > Exynos DP Initializaton was failing sometimes with unstable clock. > Changing FIMD source to resolves this issue. > > Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> At some point it would be nice to have defines for these, or even a full clock api, with clock_set_rate(), clock_set_source(), etc. Regards, Simon > --- > arch/arm/cpu/armv7/exynos/clock.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index fe61f88..bfcd5f7 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void) > */ > cfg = readl(&clk->src_disp1_0); > cfg &= ~(0xf); > - cfg |= 0x8; > + cfg |= 0x6; > writel(cfg, &clk->src_disp1_0); > > /* > -- > 1.7.1 >
Patch
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..bfcd5f7 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void) */ cfg = readl(&clk->src_disp1_0); cfg &= ~(0xf); - cfg |= 0x8; + cfg |= 0x6; writel(cfg, &clk->src_disp1_0); /*
With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)