From patchwork Sat Dec 8 13:44:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 204657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 701662C020B for ; Sun, 9 Dec 2012 01:38:34 +1100 (EST) Received: from localhost ([::1]:38104 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKjj-0006uY-Jj for incoming@patchwork.ozlabs.org; Sat, 08 Dec 2012 08:46:35 -0500 Received: from eggs.gnu.org ([208.118.235.92]:58012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKij-0005EK-TW for qemu-devel@nongnu.org; Sat, 08 Dec 2012 08:45:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ThKie-0002Ez-1J for qemu-devel@nongnu.org; Sat, 08 Dec 2012 08:45:33 -0500 Received: from cantor2.suse.de ([195.135.220.15]:36548 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKid-0002Dv-K5; Sat, 08 Dec 2012 08:45:27 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id EFA5FA4E82; Sat, 8 Dec 2012 14:44:46 +0100 (CET) From: Alexander Graf To: "qemu-ppc@nongnu.org List" Date: Sat, 8 Dec 2012 14:44:31 +0100 Message-Id: <1354974282-1915-9-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1354974282-1915-1-git-send-email-agraf@suse.de> References: <1354974282-1915-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-devel qemu-devel Subject: [Qemu-devel] [PATCH 08/19] openpic: combine openpic and mpic reset functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The openpic and mpic reset handlers are almost identical. Combine them and extract the differences into state variables. Signed-off-by: Alexander Graf --- hw/openpic.c | 103 +++++++++++++++++++++++---------------------------------- 1 files changed, 42 insertions(+), 61 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index b413bba..6a852ed 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -52,7 +52,6 @@ #define VECTOR_BITS 8 #define MAX_IPI 4 #define VID 0x03 /* MPIC version ID */ -#define VENI 0x00000000 /* Vendor ID */ enum { IRQ_IPVP = 0, @@ -124,6 +123,14 @@ enum { #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */ #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */ +#define FREP_NIRQ_SHIFT 16 +#define FREP_NCPU_SHIFT 8 +#define FREP_VID_SHIFT 0 + +#define VID_REVISION_1_2 2 + +#define VENI_GENERIC 0x00000000 /* Generic Vendor ID */ + enum mpic_ide_bits { IDR_EP = 31, IDR_CI0 = 30, @@ -207,6 +214,13 @@ typedef struct openpic_t { /* Behavior control */ uint32_t flags; + uint32_t nb_irqs; + uint32_t vid; + uint32_t veni; /* Vendor identification register */ + uint32_t spve_mask; + uint32_t tifr_reset; + uint32_t ipvp_reset; + uint32_t ide_reset; /* Sub-regions */ MemoryRegion sub_io_mem[7]; @@ -214,8 +228,6 @@ typedef struct openpic_t { /* Global registers */ uint32_t frep; /* Feature reporting register */ uint32_t glbc; /* Global configuration register */ - uint32_t micr; /* MPIC interrupt configuration register */ - uint32_t veni; /* Vendor identification register */ uint32_t pint; /* Processor initialization register */ uint32_t spve; /* Spurious vector register */ uint32_t tifr; /* Timer frequency reporting register */ @@ -234,7 +246,6 @@ typedef struct openpic_t { int max_irq; int irq_ipi0; int irq_tim0; - void (*reset) (void *); } openpic_t; static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src); @@ -411,17 +422,17 @@ static void openpic_reset (void *opaque) opp->glbc = 0x80000000; /* Initialise controller registers */ - opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; - opp->veni = VENI; + opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) | + ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) | + (opp->vid << FREP_VID_SHIFT); + opp->pint = 0x00000000; - opp->spve = 0x000000FF; - opp->tifr = 0x003F7A00; - /* ? */ - opp->micr = 0x00000000; + opp->spve = -1 & opp->spve_mask; + opp->tifr = opp->tifr_reset; /* Initialise IRQ sources */ for (i = 0; i < opp->max_irq; i++) { - opp->src[i].ipvp = 0xA0000000; - opp->src[i].ide = 0x00000000; + opp->src[i].ipvp = opp->ipvp_reset; + opp->src[i].ide = opp->ide_reset; } /* Initialise IRQ destinations */ for (i = 0; i < MAX_CPU; i++) { @@ -498,9 +509,9 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, case 0x1000: /* FREP */ break; case 0x1020: /* GLBC */ - if (val & 0x80000000 && opp->reset) - opp->reset(opp); - opp->glbc = val & ~0x80000000; + if (val & 0x80000000) { + openpic_reset(opp); + } break; case 0x1080: /* VENI */ break; @@ -529,7 +540,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, } break; case 0x10E0: /* SPVE */ - opp->spve = val & 0x000000FF; + opp->spve = val & opp->spve_mask; break; default: break; @@ -911,9 +922,7 @@ static void openpic_save(QEMUFile* f, void *opaque) openpic_t *opp = (openpic_t *)opaque; unsigned int i; - qemu_put_be32s(f, &opp->frep); qemu_put_be32s(f, &opp->glbc); - qemu_put_be32s(f, &opp->micr); qemu_put_be32s(f, &opp->veni); qemu_put_be32s(f, &opp->pint); qemu_put_be32s(f, &opp->spve); @@ -963,9 +972,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id) if (version_id != 1) return -EINVAL; - qemu_get_be32s(f, &opp->frep); qemu_get_be32s(f, &opp->glbc); - qemu_get_be32s(f, &opp->micr); qemu_get_be32s(f, &opp->veni); qemu_get_be32s(f, &opp->pint); qemu_get_be32s(f, &opp->spve); @@ -1042,6 +1049,11 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, // isu_base &= 0xFFFC0000; opp->nb_cpus = nb_cpus; + opp->nb_irqs = OPENPIC_EXT_IRQ; + opp->vid = VID; + opp->veni = VENI_GENERIC; + opp->spve_mask = 0xFF; + opp->tifr_reset = 0x003F7A00; opp->max_irq = OPENPIC_MAX_IRQ; opp->irq_ipi0 = OPENPIC_IRQ_IPI0; opp->irq_tim0 = OPENPIC_IRQ_TIM0; @@ -1067,51 +1079,12 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, openpic_save, openpic_load, opp); qemu_register_reset(openpic_reset, opp); - opp->reset = openpic_reset; - if (pmem) *pmem = &opp->mem; return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); } -static void mpic_reset (void *opaque) -{ - openpic_t *mpp = (openpic_t *)opaque; - int i; - - mpp->glbc = 0x80000000; - /* Initialise controller registers */ - mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8); - mpp->veni = VENI; - mpp->pint = 0x00000000; - mpp->spve = 0x0000FFFF; - /* Initialise IRQ sources */ - for (i = 0; i < mpp->max_irq; i++) { - mpp->src[i].ipvp = 0x80800000; - mpp->src[i].ide = 0x00000001; - } - /* Set IDE for IPIs to 0 so we don't get spurious interrupts */ - for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) { - mpp->src[i].ide = 0; - } - /* Initialise IRQ destinations */ - for (i = 0; i < MAX_CPU; i++) { - mpp->dst[i].pctp = 0x0000000F; - memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); - mpp->dst[i].raised.next = -1; - memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); - mpp->dst[i].servicing.next = -1; - } - /* Initialise timers */ - for (i = 0; i < MAX_TMR; i++) { - mpp->timers[i].ticc = 0x00000000; - mpp->timers[i].tibc = 0x80000000; - } - /* Go out of RESET state */ - mpp->glbc = 0x00000000; -} - static const MemoryRegionOps mpic_glb_ops = { .write = openpic_gbl_write, .read = openpic_gbl_read, @@ -1184,6 +1157,15 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base, } mpp->nb_cpus = nb_cpus; + /* 12 external sources, 48 internal sources , 4 timer sources, + 4 IPI sources, 4 messaging sources, and 8 Shared MSI sources */ + mpp->nb_irqs = 80; + mpp->vid = VID_REVISION_1_2; + mpp->veni = VENI_GENERIC; + mpp->spve_mask = 0xFFFF; + mpp->tifr_reset = 0x00000000; + mpp->ipvp_reset = 0x80000000; + mpp->ide_reset = 0x00000001; mpp->max_irq = MPIC_MAX_IRQ; mpp->irq_ipi0 = MPIC_IPI_IRQ; mpp->irq_tim0 = MPIC_TMR_IRQ; @@ -1194,10 +1176,9 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base, /* Enable critical interrupt support */ mpp->flags |= OPENPIC_FLAG_IDE_CRIT; - mpp->reset = mpic_reset; register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp); - qemu_register_reset(mpic_reset, mpp); + qemu_register_reset(openpic_reset, mpp); return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq); }