From patchwork Sat Dec 8 13:44:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 204648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0B7252C01C2 for ; Sun, 9 Dec 2012 00:45:55 +1100 (EST) Received: from localhost ([::1]:35353 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKj3-0005Ke-2Z for incoming@patchwork.ozlabs.org; Sat, 08 Dec 2012 08:45:53 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKig-0005Dr-7f for qemu-devel@nongnu.org; Sat, 08 Dec 2012 08:45:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ThKid-0002E1-GV for qemu-devel@nongnu.org; Sat, 08 Dec 2012 08:45:30 -0500 Received: from cantor2.suse.de ([195.135.220.15]:36535 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ThKid-0001uf-70; Sat, 08 Dec 2012 08:45:27 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 172B9A3B99; Sat, 8 Dec 2012 14:44:46 +0100 (CET) From: Alexander Graf To: "qemu-ppc@nongnu.org List" Date: Sat, 8 Dec 2012 14:44:27 +0100 Message-Id: <1354974282-1915-5-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1354974282-1915-1-git-send-email-agraf@suse.de> References: <1354974282-1915-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: qemu-devel qemu-devel Subject: [Qemu-devel] [PATCH 04/19] openpic: combine mpic and openpic src handlers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The MPIC source irq handler suddenly became identical to the standard OpenPIC source irq handler. Combine them into the same function. Signed-off-by: Alexander Graf --- hw/openpic.c | 52 +++++----------------------------------------------- 1 files changed, 5 insertions(+), 47 deletions(-) diff --git a/hw/openpic.c b/hw/openpic.c index 2776a36..0d65b71 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -99,8 +99,8 @@ enum { #define MPIC_GLB_REG_SIZE 0x10F0 #define MPIC_TMR_REG_START 0x10F0 #define MPIC_TMR_REG_SIZE 0x220 -#define MPIC_IRQ_REG_START 0x10000 -#define MPIC_IRQ_REG_SIZE (MAX_IRQ * 0x20) +#define MPIC_SRC_REG_START 0x10000 +#define MPIC_SRC_REG_SIZE (MAX_IRQ * 0x20) #define MPIC_CPU_REG_START 0x20000 #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) @@ -1168,48 +1168,6 @@ static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len) return retval; } -static void mpic_src_irq_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - openpic_t *mpp = opaque; - int idx = addr / 0x20; - - DPRINTF("%s: addr " TARGET_FMT_plx " <= %08" PRIx64 "\n", - __func__, addr, val); - if (addr & 0xF) - return; - - if (addr & 0x10) { - /* EXDE / IFEDE / IEEDE */ - write_IRQreg_ide(mpp, idx, val); - } else { - /* EXVP / IFEVP / IEEVP */ - write_IRQreg_ipvp(mpp, idx, val); - } -} - -static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len) -{ - openpic_t *mpp = opaque; - uint32_t retval; - int idx = addr / 0x20; - - DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); - if (addr & 0xF) - return -1; - - if (addr & 0x10) { - /* EXDE / IFEDE / IEEDE */ - retval = read_IRQreg_ide(mpp, idx); - } else { - /* EXVP / IFEVP / IEEVP */ - retval = read_IRQreg_ipvp(mpp, idx); - } - DPRINTF("%s: => %08x\n", __func__, retval); - - return retval; -} - static const MemoryRegionOps mpic_glb_ops = { .write = openpic_gbl_write, .read = openpic_gbl_read, @@ -1241,8 +1199,8 @@ static const MemoryRegionOps mpic_cpu_ops = { }; static const MemoryRegionOps mpic_irq_ops = { - .write = mpic_src_irq_write, - .read = mpic_src_irq_read, + .write = openpic_src_write, + .read = openpic_src_read, .endianness = DEVICE_BIG_ENDIAN, .impl = { .min_access_size = 4, @@ -1263,7 +1221,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base, } const list[] = { {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE}, {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE}, - {"irq", &mpic_irq_ops, MPIC_IRQ_REG_START, MPIC_IRQ_REG_SIZE}, + {"src", &mpic_irq_ops, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE}, {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, };