From patchwork Wed Dec 5 06:53:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [v1,1/3] xilinx_axienet: Implement R_IS behaviour Date: Tue, 04 Dec 2012 20:53:42 -0000 From: Peter Crosthwaite X-Patchwork-Id: 203792 Message-Id: <0726bd9390d5c58e61657ac42f368ecebc6cc1c3.1354690179.git.peter.crosthwaite@xilinx.com> To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Peter Crosthwaite , peter.maydell@linaro.org The interrupt status register R_IS is the standard clear-on-write behaviour. This was unimplemented and defaulting to updating the register to the written value. Implemented clear-on-write. Reported-by: Jason Wu Signed-off-by: Peter Crosthwaite --- hw/xilinx_axienet.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index baae02b..f2e3bf1 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr, s->maddr[s->fmi & 3][addr & 1] = value; break; + case R_IS: + s->regs[addr] &= ~value; + break; + case 0x8000 ... 0x83ff: s->ext_mtable[addr - 0x8000] = value; break;