From patchwork Wed Dec 5 03:15:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 203783 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8EE2A2C00AC for ; Wed, 5 Dec 2012 14:57:35 +1100 (EST) Received: from localhost ([::1]:53083 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg5TL-0008IM-Sg for incoming@patchwork.ozlabs.org; Tue, 04 Dec 2012 22:16:31 -0500 Received: from eggs.gnu.org ([208.118.235.92]:60621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg5Sg-0006Sw-4Q for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tg5Se-00029B-Tr for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:49 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:39861) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg5Se-00021d-F7 for qemu-devel@nongnu.org; Tue, 04 Dec 2012 22:15:48 -0500 Received: by mail-la0-f45.google.com with SMTP id p9so3416568laa.4 for ; Tue, 04 Dec 2012 19:15:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=OqayYQyijeZgI6iVAoXs1eHgci+SNZGk0qYqr3sOQkA=; b=WrWHE94YBWZ8tLTg6S2EzTNMuMPUwKJSlLNO1rVk6qBfD9HfJSisNKM7bIfRunUsPw phziu6V59LU7i1VaXyCy90dFTAClt3yu+FXJMbagcF3+gD1PdxDl8o4wLZc2w3txPn+P ykCfH2SPbokWf97ZwgxojIFZH9VqmN7t1yFYdxjA4KWANAqsrilfwFiQeu1n1M11nKDW itEhYhkzr2w71VxqeLEeuFC5rCl7KkNuLbpqUM1964WTQrka2n34aH3V2okWQ0WnHwjA zVa0ABfLTYAU8Hhqwt7iEZWSLEcSBIuJ5cXbq6fZ77cmwoTPPAkHrphISHyhdBPVEPoD xfIQ== Received: by 10.112.17.194 with SMTP id q2mr2965945lbd.7.1354677347871; Tue, 04 Dec 2012 19:15:47 -0800 (PST) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id er8sm1475005lbb.9.2012.12.04.19.15.46 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 04 Dec 2012 19:15:47 -0800 (PST) From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 5 Dec 2012 07:15:24 +0400 Message-Id: <1354677327-22552-6-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1354677327-22552-1-git-send-email-jcmvbkbc@gmail.com> References: <1354677327-22552-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.215.45 Cc: Blue Swirl , Max Filippov Subject: [Qemu-devel] [PATCH 5/8] target-xtensa: implement MISC SR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov --- target-xtensa/cpu.h | 1 + target-xtensa/overlay_tool.h | 1 + target-xtensa/translate.c | 4 ++++ 3 files changed, 6 insertions(+), 0 deletions(-) diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a73d32d..08fd5bc 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -153,6 +153,7 @@ enum { ICOUNTLEVEL = 237, EXCVADDR = 238, CCOMPARE = 240, + MISC = 244, }; #define PS_INTLEVEL 0xf diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index 0b47029..dd4f51a 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -95,6 +95,7 @@ /* Other, TODO */ \ XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ + XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID)) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index fbeac7f..48a22de 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -179,6 +179,10 @@ static const XtensaReg sregnames[256] = { XTENSA_OPTION_TIMER_INTERRUPT), [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", XTENSA_OPTION_TIMER_INTERRUPT), + [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), + [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), + [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), + [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), }; static const XtensaReg uregnames[256] = {