From patchwork Tue Dec 4 23:29:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 203744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B0132C00A8 for ; Wed, 5 Dec 2012 10:28:58 +1100 (EST) Received: from localhost ([::1]:44048 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg1v6-0005Nu-BZ for incoming@patchwork.ozlabs.org; Tue, 04 Dec 2012 18:28:56 -0500 Received: from eggs.gnu.org ([208.118.235.92]:39519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg1uz-0005Nk-8I for qemu-devel@nongnu.org; Tue, 04 Dec 2012 18:28:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Tg1ux-000736-EX for qemu-devel@nongnu.org; Tue, 04 Dec 2012 18:28:49 -0500 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:56024 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Tg1ux-00071n-3b for qemu-devel@nongnu.org; Tue, 04 Dec 2012 18:28:47 -0500 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id A091225B68F for ; Wed, 5 Dec 2012 00:28:44 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Wed, 5 Dec 2012 00:29:10 +0100 Message-Id: <1354663750-2163-1-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.5.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 Cc: blauwirbel@gmail.com, petarj@mips.com, rth7680@gmail.com, afaerber@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO and SHILOV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic Reviewed-by: Eric Johnson Reviewed-by: Richard Henderson --- target-mips/dsp_helper.c | 17 +++++++++-------- tests/tcg/mips/mips32-dsp/shilo.c | 18 ++++++++++++++++++ tests/tcg/mips/mips32-dsp/shilov.c | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e7949c2..44f6dc7 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env) rs5_0 = rs & 0x3F; rs5_0 = (int8_t)(rs5_0 << 2) >> 2; - rs5_0 = MIPSDSP_ABS(rs5_0); + + if (unlikely(rs5_0 == 0)) { + return; + } + acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); - if (rs5_0 == 0) { - temp = acc; + + if (rs5_0 > 0) { + temp = acc >> rs5_0; } else { - if (rs5_0 > 0) { - temp = acc >> rs5_0; - } else { - temp = acc << rs5_0; - } + temp = acc << -rs5_0; } env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c index b686616..ce8ebc6 100644 --- a/tests/tcg/mips/mips32-dsp/shilo.c +++ b/tests/tcg/mips/mips32-dsp/shilo.c @@ -23,5 +23,23 @@ int main() assert(ach == resulth); assert(acl == resultl); + + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilo $ac1, -1\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; } diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c index f186032..e1d6cea 100644 --- a/tests/tcg/mips/mips32-dsp/shilov.c +++ b/tests/tcg/mips/mips32-dsp/shilov.c @@ -25,5 +25,25 @@ int main() assert(ach == resulth); assert(acl == resultl); + + rs = 0xffffffff; + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; }