From patchwork Tue Dec 4 07:36:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shaohui xie X-Patchwork-Id: 203583 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 34EB42C0092 for ; Tue, 4 Dec 2012 19:41:08 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 481D54A10E; Tue, 4 Dec 2012 09:41:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bJjCqdRVgN7Y; Tue, 4 Dec 2012 09:41:05 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E0BE54A105; Tue, 4 Dec 2012 09:41:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C90734A105 for ; Tue, 4 Dec 2012 09:40:59 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3NxSmZJrY1i2 for ; Tue, 4 Dec 2012 09:40:58 +0100 (CET) X-Greylist: delayed 905 seconds by postgrey-1.27 at theia; Tue, 04 Dec 2012 09:40:57 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe005.messaging.microsoft.com [216.32.180.31]) by theia.denx.de (Postfix) with ESMTPS id 97FEE4A100 for ; Tue, 4 Dec 2012 09:40:57 +0100 (CET) Received: from mail210-va3-R.bigfish.com (10.7.14.252) by VA3EHSOBE014.bigfish.com (10.7.40.64) with Microsoft SMTP Server id 14.1.225.23; Tue, 4 Dec 2012 08:25:50 +0000 Received: from mail210-va3 (localhost [127.0.0.1]) by mail210-va3-R.bigfish.com (Postfix) with ESMTP id 1B331580192 for ; Tue, 4 Dec 2012 08:25:50 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1de0h1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1155h) Received: from mail210-va3 (localhost.localdomain [127.0.0.1]) by mail210-va3 (MessageSwitch) id 1354609548642301_1013; Tue, 4 Dec 2012 08:25:48 +0000 (UTC) Received: from VA3EHSMHS020.bigfish.com (unknown [10.7.14.249]) by mail210-va3.bigfish.com (Postfix) with ESMTP id 8F001B40051 for ; Tue, 4 Dec 2012 08:25:48 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS020.bigfish.com (10.7.99.30) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 4 Dec 2012 08:25:40 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.318.3; Tue, 4 Dec 2012 08:25:39 +0000 Received: from localhost.localdomain (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id qB48PW1p021025; Tue, 4 Dec 2012 01:25:37 -0700 From: Shaohui Xie To: Date: Tue, 4 Dec 2012 15:36:32 +0800 Message-ID: <1354606592-28179-1-git-send-email-Shaohui.Xie@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Shaohui Xie Subject: [U-Boot] [PATCH] powerpc/p2041: move Lanes mux to board early init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Lanes mux currently is configured in eth.c when initializing FMAN ethernet ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to p2041rdb.c which implements a board-specific initialization and will be called at early stage. Signed-off-by: Shaohui Xie --- board/freescale/p2041rdb/eth.c | 39 ------------------------------- board/freescale/p2041rdb/p2041rdb.c | 44 +++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 39 deletions(-) diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index fec9777..4b0d577 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -136,11 +136,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } #endif /* #ifdef CONFIG_FMAN_ENET */ -#define CPLD_LANE_A_SEL 0x1 -#define CPLD_LANE_G_SEL 0x2 -#define CPLD_LANE_C_SEL 0x4 -#define CPLD_LANE_D_SEL 0x8 - int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET @@ -148,10 +143,6 @@ int board_eth_init(bd_t *bis) struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - int srds_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; - u8 mux = CPLD_READ(serdes_mux); printf("Initializing Fman\n"); @@ -181,36 +172,6 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL); - switch (srds_prtcl) { - case 0x2: - case 0xf: - mux &= ~CPLD_LANE_G_SEL; - break; - case 0x5: - case 0x9: - case 0xa: - case 0x17: - mux |= CPLD_LANE_G_SEL; - break; - case 0x14: - mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL; - break; - case 0x8: - case 0x16: - case 0x19: - case 0x1a: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; - break; - case 0x1c: - mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; - break; - default: - printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); - break; - } - CPLD_WRITE(serdes_mux, mux); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 51c4310..3bda09c 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -105,6 +105,49 @@ int board_early_init_f(void) return 0; } +#define CPLD_LANE_A_SEL 0x1 +#define CPLD_LANE_G_SEL 0x2 +#define CPLD_LANE_C_SEL 0x4 +#define CPLD_LANE_D_SEL 0x8 + +void board_config_lanes_mux(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + u8 mux = 0; + switch (srds_prtcl) { + case 0x2: + case 0x5: + case 0x9: + case 0xa: + case 0xf: + break; + case 0x8: + mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x14: + mux |= CPLD_LANE_A_SEL; + break; + case 0x17: + mux |= CPLD_LANE_G_SEL; + break; + case 0x16: + case 0x19: + case 0x1a: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; + break; + case 0x1c: + mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; + break; + default: + printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + CPLD_WRITE(serdes_mux, mux); +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -128,6 +171,7 @@ int board_early_init_r(void) set_liodns(); setup_portals(); + board_config_lanes_mux(); return 0; }