Patchwork [U-Boot,v2,08/10] NET: mvgbe: add support for Dove

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Submitter Sebastian Hesselbarth
Date Dec. 4, 2012, 8:32 a.m.
Message ID <1354609923-27320-9-git-send-email-sebastian.hesselbarth@gmail.com>
Download mbox | patch
Permalink /patch/203580/
State Accepted
Delegated to: Joe Hershberger
Headers show

Comments

Sebastian Hesselbarth - Dec. 4, 2012, 8:32 a.m.
Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---
Cc: u-boot@lists.denx.de
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Daniel Stodden <daniel.stodden@gmail.com>
Cc: Luka Perkov <luka@openwrt.org>
---
 drivers/net/mvgbe.c |    2 ++
 drivers/net/mvgbe.h |    7 +++++++
 2 files changed, 9 insertions(+)
Joe Hershberger - July 8, 2013, 4 p.m.
On Tue, Dec 4, 2012 at 2:32 AM, Sebastian Hesselbarth
<sebastian.hesselbarth@gmail.com> wrote:
> Marvell Dove also uses mvgbe as ethernet driver, therefore add support
> for Dove to reuse the current driver.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Applied, Thanks.
-Joe

Patch

diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 192c989..590ea0b 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@ 
 #include <asm/arch/kirkwood.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_DOVE)
+#include <asm/arch/dove.h>
 #endif
 
 #include "mvgbe.h"
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..7f5d98f 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,17 @@ 
 #define EBAR_TARGET_GUNIT			0x00000007
 
 /* Window attrib */
+#if defined(CONFIG_DOVE)
+#define EBAR_DRAM_CS0				0x00000000
+#define EBAR_DRAM_CS1				0x00000000
+#define EBAR_DRAM_CS2				0x00000000
+#define EBAR_DRAM_CS3				0x00000000
+#else
 #define EBAR_DRAM_CS0				0x00000E00
 #define EBAR_DRAM_CS1				0x00000D00
 #define EBAR_DRAM_CS2				0x00000B00
 #define EBAR_DRAM_CS3				0x00000700
+#endif
 
 /* DRAM Target interface */
 #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000