From patchwork Tue Dec 4 00:26:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 203513 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1E2A72C008D for ; Tue, 4 Dec 2012 11:26:22 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4E8284A0FC; Tue, 4 Dec 2012 01:26:20 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zQ+6TDaIchZ2; Tue, 4 Dec 2012 01:26:20 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 470664A0FF; Tue, 4 Dec 2012 01:26:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0DD114A0FF for ; Tue, 4 Dec 2012 01:26:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z9poe2Yc9yRN for ; Tue, 4 Dec 2012 01:26:14 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bk0-f74.google.com (mail-bk0-f74.google.com [209.85.214.74]) by theia.denx.de (Postfix) with ESMTPS id 984874A0FC for ; Tue, 4 Dec 2012 01:26:12 +0100 (CET) Received: by mail-bk0-f74.google.com with SMTP id je9so405804bkc.3 for ; Mon, 03 Dec 2012 16:26:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=StBpfOO9AkGU3jj8OzxkeELSag8gchlWuGJIYbK+hPQ=; b=dX8lNpe2Uw7L6wZpZ74sDh+eQl2fQt2qSkhkFkzmHQDPJFuZwQDivG+a7lAOx/qe32 u+In3QSdz+VjNN/asZ9kVuSLeQlbLX2Axe70ltqfTe+CaO5jMrU+kaFUpa9PSTirNO+m 0lCsd8VaoMyyVxjZyx93+ds03JIOgCdlPhVNq7wGaZl+gVNN3mih0YiqWQyAwhLOpXkk Gk0dAtfJArUC1ti21I7VAqOrraxwK2ZqLT6zbzEvRakURUllIRKb78q5wzLbGhuZ46Cf gPAHHMFwGuW8ebK6wPCkadQOqZojECmFPYOP2ck2b4Tf4mOfAaLiMCeosvmR8rmOXGlU URqA== Received: by 10.14.204.199 with SMTP id h47mr3368689eeo.4.1354580771293; Mon, 03 Dec 2012 16:26:11 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id u8si3554556een.1.2012.12.03.16.26.11 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 03 Dec 2012 16:26:11 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id E2E3420004E; Mon, 3 Dec 2012 16:26:10 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 2AC4F1605D9; Mon, 3 Dec 2012 16:26:10 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 3 Dec 2012 16:26:08 -0800 Message-Id: <1354580768-12118-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1351978902-23719-6-git-send-email-sjg@chromium.org> References: <1351978902-23719-6-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmc+dApdSQNuqkhozYcQBQkLD9UIgWZob2rkpaalu2Wt1sS/Z3sExxe4RpjjqyJ/d61IcHE3G0kev0xAs7RXGiVUimiapZtp2WZnR++QfgJxqR9rgIXDArWPRhCy8MY5Lxyy8spuUFeXvYUL/tkkyuirVWeY+lPykZYY2CU5AwqELm2HuA/Suiu4ekx4Cp55MnPxMx4 Subject: [U-Boot] [PATCH v2 05/21] x86: Override calculate_relocation_address to use the e820 map X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Gabe Black Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- Changes in v2: - Update relocation for new link symbols, headers - Update relocation for new global data positioning - Update coreboot text base to fit with relocation scheme arch/x86/cpu/coreboot/sdram.c | 61 +++++++++++++++++++++++++++++++++++++---- boards.cfg | 2 +- 2 files changed, 56 insertions(+), 7 deletions(-) diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index 5d3da99..76274cb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -27,8 +27,9 @@ #include #include #include -#include -#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -51,6 +52,58 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) return num_entries; } +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. It + * overrides the default implementation found elsewhere which simply picks the + * end of ram, wherever that may be. The location of the stack, the relocation + * address, and how far U-Boot is moved by relocation are set in the global + * data structure. + */ +int calculate_relocation_address(void) +{ + const uint64_t uboot_size = (uintptr_t)&__bss_end - + (uintptr_t)&__text_start; + const uint64_t total_size = uboot_size + CONFIG_SYS_MALLOC_LEN + + CONFIG_SYS_STACK_SIZE; + uintptr_t dest_addr = 0; + int i; + + for (i = 0; i < lib_sysinfo.n_memranges; i++) { + struct memrange *memrange = &lib_sysinfo.memrange[i]; + /* Force U-Boot to relocate to a page aligned address. */ + uint64_t start = roundup(memrange->base, 1 << 12); + uint64_t end = memrange->base + memrange->size; + + /* Ignore non-memory regions. */ + if (memrange->type != CB_MEM_RAM) + continue; + + /* Filter memory over 4GB. */ + if (end > 0xffffffffULL) + end = 0x100000000ULL; + /* Skip this region if it's too small. */ + if (end - start < total_size) + continue; + + /* Use this address if it's the largest so far. */ + if (end - uboot_size > dest_addr) + dest_addr = end; + } + + /* If no suitable area was found, return an error. */ + if (!dest_addr) + return 1; + + dest_addr -= uboot_size; + dest_addr &= ~((1 << 12) - 1); + gd->relocaddr = dest_addr; + gd->reloc_off = dest_addr - (uintptr_t)&__text_start; + gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN; + + return 0; +} + int dram_init_f(void) { int i; @@ -60,10 +113,6 @@ int dram_init_f(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size; - /* Ignore memory over 4GB, we can't use it. */ - if (memrange->base > 0xffffffff) - continue; - if (memrange->type == CB_MEM_RAM && end > ram_size) ram_size = end; } diff --git a/boards.cfg b/boards.cfg index ca9b12b..9093ecb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1099,7 +1099,7 @@ gr_cpci_ax2000 sparc leon3 - gaisler gr_ep2s60 sparc leon3 - gaisler grsim sparc leon3 - gaisler gr_xc3s_1500 sparc leon3 - gaisler -coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000 +coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000 eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000 eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000 # Target ARCH CPU Board name Vendor SoC Options