From patchwork Mon Dec 3 23:59:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 203506 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 12C772C0095 for ; Tue, 4 Dec 2012 10:59:32 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C5FEB4A149; Tue, 4 Dec 2012 00:59:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L+iks5G9IEuh; Tue, 4 Dec 2012 00:59:30 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 18D2E4A11E; Tue, 4 Dec 2012 00:59:29 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E1BF4A11E for ; Tue, 4 Dec 2012 00:59:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O-PcYpzPn7qH for ; Tue, 4 Dec 2012 00:59:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-lb0-f202.google.com (mail-lb0-f202.google.com [209.85.217.202]) by theia.denx.de (Postfix) with ESMTPS id 9237C4A118 for ; Tue, 4 Dec 2012 00:59:25 +0100 (CET) Received: by mail-lb0-f202.google.com with SMTP id s4so94897lbc.3 for ; Mon, 03 Dec 2012 15:59:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Swj1SlZixM/19I7mrtdDjgg6RHZsKh9ejRA+/D1srAQ=; b=bLwS71kuNpjqsHDyfAC8BDYt6kINBSky2EVSIxCv6veMihO8mvubiygKBMjxPDCpsf scG/Oh47OqpQv+82iTAwsnCJ9dUABzIyIRLQMlzjZ9dEe93CNgT11i768Q4m6cSdgTiF Bgo3iI/XuzE3+BgwISfBbe662NJvMqfOPn10gbWMYdTHFuCRsa5seHvRMfdbGFFwr5OT 8i/wK7D/kYlIsHK6DTl0Ge1knZLAJOsuUmnZPi+oiE3A/2FlG+c6GvcW+/cNdOXMnuGH XfaSM+UOu0uZkPGfuZHTQQfSpXzJkTCakTLf/zOZHA7WfWva872DQPp37mJwbXZJAZke RI5Q== Received: by 10.14.216.197 with SMTP id g45mr12118029eep.3.1354579164532; Mon, 03 Dec 2012 15:59:24 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id u8si3543351een.1.2012.12.03.15.59.24 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 03 Dec 2012 15:59:24 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id 2E4AE20004E; Mon, 3 Dec 2012 15:59:24 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 8D552160351; Mon, 3 Dec 2012 15:59:23 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 3 Dec 2012 15:59:20 -0800 Message-Id: <1354579160-2410-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1351978902-23719-15-git-send-email-sjg@chromium.org> References: <1351978902-23719-15-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkb0B9p4NNqxRhvlvApGy1P9oR2w+wTylnYkpt2+4DE0y2nuH0IErweu/0kf68pkUNuzjt5w5gACJ6139N0oqdZ4z5GHf8xCaiFjp+mMCCuraxbGHXm4wlulQOU9tKuhoU660NrdVr6EW/m2wNJFiKcwv7JfXN5N+/lM59qF8goVuLtWc6q4Obg38Ged1tcgeJ2wRNm Cc: Vadim Bendebury Subject: [U-Boot] [PATCH v2 14/21] x86: Provide tick counter and frequency reference for Intel core architecture X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Vadim Bendebury Some u-boot modules rely on availability of get_ticks() and get_tbclk() functions, reporting a free running clock and its frequency respectively. Traditionally these functions return number and frequency of timer interrupts. Intel's core architecture processors however are known to run the rdtsc instruction at a constant rate of the so called 'Max Non Turbo ratio' times the external clock frequency which is 100MHz. This is just as good for the timer tick functions in question. Signed-off-by: Vadim Bendebury Signed-off-by: Simon Glass --- Changes in v2: - Use functions from Graeme's msr patch arch/x86/cpu/interrupts.c | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index e788715..dd30a05 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -34,6 +34,8 @@ #include #include #include +#include +#include #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -615,3 +617,32 @@ asm(".globl irq_common_entry\n" \ DECLARE_INTERRUPT(253) \ DECLARE_INTERRUPT(254) \ DECLARE_INTERRUPT(255)); + +#if defined(CONFIG_INTEL_CORE_ARCH) +/* + * Get the number of CPU time counter ticks since it was read first time after + * restart. This yields a free running counter guaranteed to take almost 6 + * years to wrap around even at 100GHz clock rate. + */ +u64 get_ticks(void) +{ + static u64 tick_base; + u64 now_tick = rdtsc(); + + if (!tick_base) + tick_base = now_tick; + + return now_tick - tick_base; +} + +#define PLATFORM_INFO_MSR 0xce + +unsigned long get_tbclk(void) +{ + u32 ratio; + u64 platform_info = native_read_msr(PLATFORM_INFO_MSR); + + ratio = (platform_info >> 8) & 0xff; + return 100 * 1000 * 1000 * ratio; /* 100MHz times Max Non Turbo ratio */ +} +#endif