From patchwork Mon Dec 3 23:56:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 203503 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E66F32C00A3 for ; Tue, 4 Dec 2012 10:57:47 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 730834A11D; Tue, 4 Dec 2012 00:57:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h-vryQ57fRwS; Tue, 4 Dec 2012 00:57:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E195A4A0F9; Tue, 4 Dec 2012 00:57:41 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 67C504A0F9 for ; Tue, 4 Dec 2012 00:57:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id o-AoSmQmn1jb for ; Tue, 4 Dec 2012 00:57:38 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gh0-f202.google.com (mail-gh0-f202.google.com [209.85.160.202]) by theia.denx.de (Postfix) with ESMTPS id 40EF44A0C1 for ; Tue, 4 Dec 2012 00:57:36 +0100 (CET) Received: by mail-gh0-f202.google.com with SMTP id z10so474003ghb.3 for ; Mon, 03 Dec 2012 15:57:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=fbLng6JvmGvPVg2Pu+Ma3dDH4CXpljN+iERucO8uO40=; b=exGgeNkrtLYq69hYFIOSM89xFiikfMkFqWHKpT2NPLu76/0XGycYrxLmvAqz9P4eTt oeDb1ZOaE6dOWKG5o2ipo6y4bxPv4UdEPJq+z1DZbk7kdk9ft8ruKtZHAN7EcEZwHrFl GO1SmuGsAn0FVMQax72LGj+AuUSKv7rytEBGWxlZgLBnnPyCUST8xkKOZ3AsXDVMjMT1 LqRyXNaPsyPGL0Wx3PVAyxigS4+Fte1wNCN3iYezNoipHoBEq6Fj0SqvByTC0q1x4cQV kkuoS8yICzcGPtWtgvCC91Dj1IoU83VXRl72J8bpu0QzVvzcanQMH8plnajCYeFR/loT 0FHA== Received: by 10.101.64.17 with SMTP id r17mr1958428ank.13.1354579055397; Mon, 03 Dec 2012 15:57:35 -0800 (PST) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id s78si59193yhh.3.2012.12.03.15.57.35 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 03 Dec 2012 15:57:35 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 2A5B982004A; Mon, 3 Dec 2012 15:57:35 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id BE18816081F; Mon, 3 Dec 2012 15:57:34 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 3 Dec 2012 15:56:51 -0800 Message-Id: <1354579011-2039-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1351978902-23719-11-git-send-email-sjg@chromium.org> References: <1351978902-23719-11-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmpYsqRG/x5cd5MHTJ7wt2MA7buflCck5X3qbtmbSEs1utmEOQ4EYDzAeS+sW4bKHvtCIIUx3acmdRgv1KuCi3tcIHXzDSlYUdokM/X1P1miPzuaLSzI5fixnktNo6AyYKOu2bxLxTV+RwGKdwiuCMdbPBmzclM7ZvfHkCTRaWnIqrMB86jNfo91JW38pZuVwHkq2k4 Cc: Stefan Reinauer Subject: [U-Boot] [PATCH v2 10/21] x86: fdt: Create basic .dtsi file for coreboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- Changes in v2: - Update alex to use this include file - Add an empty link .dts which also uses this include file arch/x86/dts/coreboot.dtsi | 16 +++++++++++++ arch/x86/dts/skeleton.dtsi | 13 ++++++++++ .../chromebook-x86/dts/{x86-alex.dts => alex.dts} | 18 +++++---------- board/chromebook-x86/dts/link.dts | 24 ++++++++++++++++++++ 4 files changed, 59 insertions(+), 12 deletions(-) create mode 100644 arch/x86/dts/coreboot.dtsi create mode 100644 arch/x86/dts/skeleton.dtsi rename board/chromebook-x86/dts/{x86-alex.dts => alex.dts} (53%) create mode 100644 board/chromebook-x86/dts/link.dts diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi new file mode 100644 index 0000000..4862a59 --- /dev/null +++ b/arch/x86/dts/coreboot.dtsi @@ -0,0 +1,16 @@ +/include/ "skeleton.dtsi" + +/ { + aliases { + console = "/serial"; + }; + + serial { + compatible = "ns16550"; + reg-shift = <1>; + io-mapped = <1>; + multiplier = <1>; + baudrate = <115200>; + status = "disabled"; + }; +}; diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi new file mode 100644 index 0000000..b41d241 --- /dev/null +++ b/arch/x86/dts/skeleton.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/board/chromebook-x86/dts/x86-alex.dts b/board/chromebook-x86/dts/alex.dts similarity index 53% rename from board/chromebook-x86/dts/x86-alex.dts rename to board/chromebook-x86/dts/alex.dts index bd90d18..cb6a9e4 100644 --- a/board/chromebook-x86/dts/x86-alex.dts +++ b/board/chromebook-x86/dts/alex.dts @@ -1,5 +1,7 @@ /dts-v1/; +/include/ "coreboot.dtsi" + / { #address-cells = <1>; #size-cells = <1>; @@ -10,19 +12,11 @@ silent_console = <0>; }; - aliases { - console = "/serial@e0401000"; - }; + gpio: gpio {}; - serial@e0401000 { - compatible = "ns16550"; - reg = <0xe0401000 0x40>; - id = <1>; - reg-shift = <1>; - baudrate = <115200>; - clock-frequency = <4000000>; - multiplier = <1>; - status = "ok"; + serial { + reg = <0x3f8 8>; + clock-frequency = <115200>; }; chosen { }; diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts new file mode 100644 index 0000000..af60f59 --- /dev/null +++ b/board/chromebook-x86/dts/link.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "coreboot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Google Link"; + compatible = "google,link", "intel,celeron-ivybridge"; + + config { + silent_console = <0>; + }; + + gpio: gpio {}; + + serial { + reg = <0x3f8 8>; + clock-frequency = <115200>; + }; + + chosen { }; + memory { device_type = "memory"; reg = <0 0>; }; +};