diff mbox

[U-Boot,v2,7/7] Tegra30: Add/enable Cardhu build (T30 reference board)

Message ID 1354578322-1834-8-git-send-email-twarren@nvidia.com
State Superseded
Delegated to: Tom Warren
Headers show

Commit Message

Tom Warren Dec. 3, 2012, 11:45 p.m. UTC 
This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.

include/configs/tegra-common.h now holds common config options
for Tegra SoCs.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
V2:
* Move pinmux_init to cardhu.c, move pinmux-config header here, too.
* tegra-common.h holds CONFIG options/defines commmon to all Tegra SoCs.

 board/nvidia/cardhu/Makefile               |   44 ++++
 board/nvidia/cardhu/cardhu.c               |   39 ++++
 board/nvidia/cardhu/pinmux-config-cardhu.h |  339 ++++++++++++++++++++++++++++
 boards.cfg                                 |    1 +
 include/configs/cardhu.h                   |   52 +++++
 include/configs/tegra-common.h             |  163 +++++++++++++
 include/configs/tegra20-common.h           |  171 ++------------
 include/configs/tegra30-common.h           |   54 +++++
 8 files changed, 716 insertions(+), 147 deletions(-)
 create mode 100644 board/nvidia/cardhu/Makefile
 create mode 100644 board/nvidia/cardhu/cardhu.c
 create mode 100644 board/nvidia/cardhu/pinmux-config-cardhu.h
 create mode 100644 include/configs/cardhu.h
 create mode 100644 include/configs/tegra-common.h
 create mode 100644 include/configs/tegra30-common.h

Comments

Stephen Warren Dec. 4, 2012, 12:53 a.m. UTC | #1 
On 12/03/2012 04:45 PM, Tom Warren wrote:
> This build is stripped down. It boots to the command prompt.
> GPIO is the only peripheral supported. Others TBD.
> 
> include/configs/tegra-common.h now holds common config options
> for Tegra SoCs.

> diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c

> +void pinmux_init(void)
> +{
> +	pinmux_config_table(tegra3_pinmux_common,
> +		ARRAY_SIZE(tegra3_pinmux_common));
> +
> +	pinmux_config_table(unused_pins_lowpower,
> +		ARRAY_SIZE(unused_pins_lowpower));
> +}

Oh, I see. Is any of the pinmux configuration actually needed for just
the UART to work? I suppose there's not much harm just setting up the
whole configuration from the start rather than adding it piece-meal.

> diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h

> +static struct pingroup_config tegra3_pinmux_common[] = {

> +#ifdef CONFIG_SND_HDA_CODEC_REALTEK
> +	DEFAULT_PINMUX(SPDIF_IN, DAP2, DOWN, NORMAL, INPUT),
> +#else
> +	DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
> +#endif

I'm pretty sure that define will never be enabled; it was some temporary
test thing that should be removed from our downstream kernel, which is
where I assume you got this table from.

> diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h

> diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h

> +#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */

Is that correct for Tegra30?

> +#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */

I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
up that way.

In this patch, you also should move MEM_LAYOUT_ENV_SETTINGS from
tegra-common-post.h into tegraNN-common.h, or something like that.
Tom Warren Dec. 4, 2012, 8:22 p.m. UTC | #2 
Stephen,

On Mon, Dec 3, 2012 at 5:53 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/03/2012 04:45 PM, Tom Warren wrote:
>> This build is stripped down. It boots to the command prompt.
>> GPIO is the only peripheral supported. Others TBD.
>>
>> include/configs/tegra-common.h now holds common config options
>> for Tegra SoCs.
>
>> diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
>
>> +void pinmux_init(void)
>> +{
>> +     pinmux_config_table(tegra3_pinmux_common,
>> +             ARRAY_SIZE(tegra3_pinmux_common));
>> +
>> +     pinmux_config_table(unused_pins_lowpower,
>> +             ARRAY_SIZE(unused_pins_lowpower));
>> +}
>
> Oh, I see. Is any of the pinmux configuration actually needed for just
> the UART to work? I suppose there's not much harm just setting up the
> whole configuration from the start rather than adding it piece-meal.

Yep, see previous reply for an explanation of why it's done in one shot.

>
>> diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
>
>> +static struct pingroup_config tegra3_pinmux_common[] = {
>
>> +#ifdef CONFIG_SND_HDA_CODEC_REALTEK
>> +     DEFAULT_PINMUX(SPDIF_IN, DAP2, DOWN, NORMAL, INPUT),
>> +#else
>> +     DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
>> +#endif
>
> I'm pretty sure that define will never be enabled; it was some temporary
> test thing that should be removed from our downstream kernel, which is
> where I assume you got this table from.

No, this came from one of our internal T30 U-Boot branches. Not sure
where the OD (original dev) got it from.

I'll remove the REALTEK parts.

>
>> diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
>
>> diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
>
>> +#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
>
> Is that correct for Tegra30?

It was originally in tegra20-common.h, and was moved into
tegra-common.h in a batch with other thought-to-be-non-HW-specific
config defines.

Looking at the code, though, I don't see it used anywhere. It can be
removed, either in V3 of this patchset or in a clean-up round of
patches later once T30 is in.

>
>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>
> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
> up that way.

See my previous reply. In the internal U-Boot repo I ported from, PLLP
was initially set to 216MHz, then sped up to 408MHz. When this first
round of patches is in, I can address going to 408MHz first thing.

>
> In this patch, you also should move MEM_LAYOUT_ENV_SETTINGS from
> tegra-common-post.h into tegraNN-common.h, or something like that.

I can do that, or we can wait until those settings are going to be
used, i.e. once I've added peripheral support so a kernel can be found
and loaded and executed.

Tom
Lucas Stach Dec. 4, 2012, 8:40 p.m. UTC | #3 
Hi Tom,

Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
[...]
> 
> >
> >> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
> >
> > I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
> > up that way.
> 
> See my previous reply. In the internal U-Boot repo I ported from, PLLP
> was initially set to 216MHz, then sped up to 408MHz. When this first
> round of patches is in, I can address going to 408MHz first thing.
> 
Is running the PLL_P at 408MHz something which requires a lot of work?
If not, please do this and fold it into this patchset. It doesn't look
too nice adding things to upstream which have to be changed/removed
immediately after going in.

Considering that Tegra 30 support is still not really in a usable state
after this patchset and the time left until things have to get ready for
the next merge window, I suppose you could do it the right way from the
start.

Regards,
Lucas
Tom Warren Dec. 4, 2012, 9:28 p.m. UTC | #4 
Lucas,

On Tue, Dec 4, 2012 at 1:40 PM, Lucas Stach <dev@lynxeye.de> wrote:
> Hi Tom,
>
> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
> [...]
>>
>> >
>> >> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>> >
>> > I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>> > up that way.
>>
>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>> was initially set to 216MHz, then sped up to 408MHz. When this first
>> round of patches is in, I can address going to 408MHz first thing.
>>
> Is running the PLL_P at 408MHz something which requires a lot of work?
> If not, please do this and fold it into this patchset. It doesn't look
> too nice adding things to upstream which have to be changed/removed
> immediately after going in.
>
> Considering that Tegra 30 support is still not really in a usable state
> after this patchset and the time left until things have to get ready for
> the next merge window, I suppose you could do it the right way from the
> start.

I'll investigate.

Thanks,

Tom
>
> Regards,
> Lucas
>
Stephen Warren Dec. 4, 2012, 10:41 p.m. UTC | #5 
On 12/04/2012 01:40 PM, Lucas Stach wrote:
> Hi Tom,
> 
> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
> [...]
>>
>>>
>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>
>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>> up that way.
>>
>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>> was initially set to 216MHz, then sped up to 408MHz. When this first
>> round of patches is in, I can address going to 408MHz first thing.
>>
> Is running the PLL_P at 408MHz something which requires a lot of work?
> If not, please do this and fold it into this patchset. It doesn't look
> too nice adding things to upstream which have to be changed/removed
> immediately after going in.

Naively I'd have to agree here; it seems that programming the PLL for
the correct rate would probably "just work" right from the outset? After
all, if the code runs OK with the higher rate enabled a little later in
boot, I see no reason it shouldn't run OK with that exact same rate the
whole way through.
Stephen Warren Dec. 4, 2012, 10:43 p.m. UTC | #6 
On 12/04/2012 01:22 PM, Tom Warren wrote:
> Stephen,
> 
> On Mon, Dec 3, 2012 at 5:53 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 12/03/2012 04:45 PM, Tom Warren wrote:
>>> This build is stripped down. It boots to the command prompt.
>>> GPIO is the only peripheral supported. Others TBD.
>>>
>>> include/configs/tegra-common.h now holds common config options
>>> for Tegra SoCs.
...
>> In this patch, you also should move MEM_LAYOUT_ENV_SETTINGS from
>> tegra-common-post.h into tegraNN-common.h, or something like that.
> 
> I can do that, or we can wait until those settings are going to be
> used, i.e. once I've added peripheral support so a kernel can be found
> and loaded and executed.

Isn't it just cut/pasting those 5 lines (well, and the comment before
them I guess) and s/0x0/0x8/ in all the lines. It seems pretty easy to
get the right values in from the start.

Without this, it's a PITA to test bootm with this U-Boot (you can
download a kernel over serial with loady for example; something I tested
with earlier revisions of this series).
Tom Warren Dec. 5, 2012, 8:30 p.m. UTC | #7 
On Tue, Dec 4, 2012 at 3:43 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/04/2012 01:22 PM, Tom Warren wrote:
>> Stephen,
>>
>> On Mon, Dec 3, 2012 at 5:53 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 12/03/2012 04:45 PM, Tom Warren wrote:
>>>> This build is stripped down. It boots to the command prompt.
>>>> GPIO is the only peripheral supported. Others TBD.
>>>>
>>>> include/configs/tegra-common.h now holds common config options
>>>> for Tegra SoCs.
> ...
>>> In this patch, you also should move MEM_LAYOUT_ENV_SETTINGS from
>>> tegra-common-post.h into tegraNN-common.h, or something like that.
>>
>> I can do that, or we can wait until those settings are going to be
>> used, i.e. once I've added peripheral support so a kernel can be found
>> and loaded and executed.
>
> Isn't it just cut/pasting those 5 lines (well, and the comment before
> them I guess) and s/0x0/0x8/ in all the lines. It seems pretty easy to
> get the right values in from the start.
>
> Without this, it's a PITA to test bootm with this U-Boot (you can
> download a kernel over serial with loady for example; something I tested
> with earlier revisions of this series).

I'll move the MEM_LAYOUT_ENV_SETTINGS (and update the addresses) since
I'm doing a V3.

Also, WRT the 408MHz tweak, I got it working w/relatively little pain.
That'll also be the de facto PLLP speed for T30 in V3 of the patchset.

Thanks,

Tom
Simon Glass Dec. 8, 2012, 8 p.m. UTC | #8 
Hi,

On Tue, Dec 4, 2012 at 2:41 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 12/04/2012 01:40 PM, Lucas Stach wrote:
>> Hi Tom,
>>
>> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
>> [...]
>>>
>>>>
>>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>>
>>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>>> up that way.
>>>
>>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>>> was initially set to 216MHz, then sped up to 408MHz. When this first
>>> round of patches is in, I can address going to 408MHz first thing.
>>>
>> Is running the PLL_P at 408MHz something which requires a lot of work?
>> If not, please do this and fold it into this patchset. It doesn't look
>> too nice adding things to upstream which have to be changed/removed
>> immediately after going in.
>
> Naively I'd have to agree here; it seems that programming the PLL for
> the correct rate would probably "just work" right from the outset? After
> all, if the code runs OK with the higher rate enabled a little later in
> boot, I see no reason it shouldn't run OK with that exact same rate the
> whole way through.

From memory, the problem was originally that we wanted to be able to
configure the PLL speed at run time, because we we using both speeds.
Since T30 now apparently only uses 408MHz, it should be ok to set it
once and hard-code it.

Regards,
Simon

>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Tom Warren Dec. 10, 2012, 5:05 p.m. UTC | #9 
Simon,

On Sat, Dec 8, 2012 at 1:00 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi,
>
> On Tue, Dec 4, 2012 at 2:41 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 12/04/2012 01:40 PM, Lucas Stach wrote:
>>> Hi Tom,
>>>
>>> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
>>> [...]
>>>>
>>>>>
>>>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>>>
>>>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>>>> up that way.
>>>>
>>>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>>>> was initially set to 216MHz, then sped up to 408MHz. When this first
>>>> round of patches is in, I can address going to 408MHz first thing.
>>>>
>>> Is running the PLL_P at 408MHz something which requires a lot of work?
>>> If not, please do this and fold it into this patchset. It doesn't look
>>> too nice adding things to upstream which have to be changed/removed
>>> immediately after going in.
>>
>> Naively I'd have to agree here; it seems that programming the PLL for
>> the correct rate would probably "just work" right from the outset? After
>> all, if the code runs OK with the higher rate enabled a little later in
>> boot, I see no reason it shouldn't run OK with that exact same rate the
>> whole way through.
>
> From memory, the problem was originally that we wanted to be able to
> configure the PLL speed at run time, because we we using both speeds.
> Since T30 now apparently only uses 408MHz, it should be ok to set it
> once and hard-code it.
>
> Regards,
> Simon
>
Thanks. As I remember it, it was a user-config option for early T30
boards to run at 216MHz or 408MHz. The 408MHz PLLP change generated a
lot of email traffic on what the best output clocks (pllp_out1 thru 4)
would be for the various periphs, subclocks, etc.

When I did the original bringup for upstream U-Boot on my (older)
Cardhu, I wanted to start at 216MHz first, then step up to 408MHz when
I was at a stable point. Much like when I rebuilt my Mustang - I took
it out around the block first, to be sure everything was working OK
before I took it on the highway ;)

I'm running OK at 408MHz on my Cardhu T33. I'll resubmit V3 of the
patchset in the next day or so.

Thanks,

Tom
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
Simon Glass Dec. 10, 2012, 7:04 p.m. UTC | #10 
Hi Tom,

On Mon, Dec 10, 2012 at 9:05 AM, Tom Warren <twarren.nvidia@gmail.com> wrote:
> Simon,
>
> On Sat, Dec 8, 2012 at 1:00 PM, Simon Glass <sjg@chromium.org> wrote:
>> Hi,
>>
>> On Tue, Dec 4, 2012 at 2:41 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>>> On 12/04/2012 01:40 PM, Lucas Stach wrote:
>>>> Hi Tom,
>>>>
>>>> Am Dienstag, den 04.12.2012, 13:22 -0700 schrieb Tom Warren:
>>>> [...]
>>>>>
>>>>>>
>>>>>>> +#define V_NS16550_CLK                        216000000       /* 216MHz (pllp_out0) */
>>>>>>
>>>>>> I thought PLL_P ran at 408MHz on Tegra30? The kernel certainly sets it
>>>>>> up that way.
>>>>>
>>>>> See my previous reply. In the internal U-Boot repo I ported from, PLLP
>>>>> was initially set to 216MHz, then sped up to 408MHz. When this first
>>>>> round of patches is in, I can address going to 408MHz first thing.
>>>>>
>>>> Is running the PLL_P at 408MHz something which requires a lot of work?
>>>> If not, please do this and fold it into this patchset. It doesn't look
>>>> too nice adding things to upstream which have to be changed/removed
>>>> immediately after going in.
>>>
>>> Naively I'd have to agree here; it seems that programming the PLL for
>>> the correct rate would probably "just work" right from the outset? After
>>> all, if the code runs OK with the higher rate enabled a little later in
>>> boot, I see no reason it shouldn't run OK with that exact same rate the
>>> whole way through.
>>
>> From memory, the problem was originally that we wanted to be able to
>> configure the PLL speed at run time, because we we using both speeds.
>> Since T30 now apparently only uses 408MHz, it should be ok to set it
>> once and hard-code it.
>>
>> Regards,
>> Simon
>>
> Thanks. As I remember it, it was a user-config option for early T30
> boards to run at 216MHz or 408MHz. The 408MHz PLLP change generated a
> lot of email traffic on what the best output clocks (pllp_out1 thru 4)
> would be for the various periphs, subclocks, etc.
>
> When I did the original bringup for upstream U-Boot on my (older)
> Cardhu, I wanted to start at 216MHz first, then step up to 408MHz when
> I was at a stable point. Much like when I rebuilt my Mustang - I took
> it out around the block first, to be sure everything was working OK
> before I took it on the highway ;)
>
> I'm running OK at 408MHz on my Cardhu T33. I'll resubmit V3 of the
> patchset in the next day or so.

Sounds good, thanks. It would be good to get this in.

Regards,
Simon

>
> Thanks,
>
> Tom
>>>
>>> _______________________________________________
>>> U-Boot mailing list
>>> U-Boot@lists.denx.de
>>> http://lists.denx.de/mailman/listinfo/u-boot
diff mbox

Patch

diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 0000000..913f1ce
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,44 @@ 
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
new file mode 100644
index 0000000..df4cb6b
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c
@@ -0,0 +1,39 @@ 
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_config_table(tegra3_pinmux_common,
+		ARRAY_SIZE(tegra3_pinmux_common));
+
+	pinmux_config_table(unused_pins_lowpower,
+		ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 0000000..df85fe1
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,339 @@ 
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PINMUX_CONFIG_COMMON_H_
+#define _TEGRA30_PINMUX_CONFIG_COMMON_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)	\
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= PINGRP_##_pingroup,		\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.lock		= PMUX_PIN_LOCK_##_lock,	\
+		.od		= PMUX_PIN_OD_DEFAULT,		\
+		.ioreset	= PMUX_PIN_IO_RESET_##_ioreset	\
+	}
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+	/* SDMMC4 pinmux */
+	LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	/* Power I2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+	DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+	LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+	DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+	DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+	DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+	DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+	/* KBC keys */
+	DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+
+	DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+#ifdef CONFIG_SND_HDA_CODEC_REALTEK
+	DEFAULT_PINMUX(SPDIF_IN, DAP2, DOWN, NORMAL, INPUT),
+#else
+	DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+#endif
+	DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+#ifdef CONFIG_SND_HDA_CODEC_REALTEK
+	DEFAULT_PINMUX(DAP2_FS, HDA, DOWN, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN, HDA, DOWN, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, HDA, DOWN, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, HDA, DOWN, NORMAL, INPUT),
+#else
+	DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+#endif
+	DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+	/* Gpios */
+	/* SDMMC1 CD gpio */
+	DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+	/* SDMMC1 WP gpio */
+	LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+	/* Touch panel GPIO */
+	/* Touch IRQ */
+	DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+	/* Touch RESET */
+	DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+	/* Power rails GPIO */
+	DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+	DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+	LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+	LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+	DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+	DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+	DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+	DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _TEGRA30_PINMUX_CONFIG_COMMON_H_ */
diff --git a/boards.cfg b/boards.cfg
index 6f21af0..01fd77f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -287,6 +287,7 @@  harmony                      arm         armv7:arm720t harmony           nvidia
 seaboard                     arm         armv7:arm720t seaboard          nvidia         tegra20
 ventana                      arm         armv7:arm720t ventana           nvidia         tegra20
 whistler                     arm         armv7:arm720t whistler          nvidia         tegra20
+cardhu                       arm         armv7:arm720t cardhu            nvidia         tegra30
 colibri_t20_iris             arm         armv7:arm720t colibri_t20_iris  toradex        tegra20
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 snowball                     arm         armv7       snowball               st-ericsson    u8500
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
new file mode 100644
index 0000000..bfadbff
--- /dev/null
+++ b/include/configs/cardhu.h
@@ -0,0 +1,52 @@ 
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
new file mode 100644
index 0000000..2821865
--- /dev/null
+++ b/include/configs/tegra-common.h
@@ -0,0 +1,163 @@ 
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_COMMON_H_
+#define _TEGRA_COMMON_H_
+#include <asm/sizes.h>
+#include <linux/stringify.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA			/* which is a Tegra generic machine */
+#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#include <asm/arch/tegra.h>		/* get chip and board defs */
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+
+/*
+ * PllX Configuration
+ */
+#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS		/* NFS support */
+#undef CONFIG_CMD_NET		/* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_TEGRA_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_ENTERRCM
+#define CONFIG_CMD_BOOTZ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index efd92e0..44c41fc 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -21,34 +21,38 @@ 
  * MA 02111-1307 USA
  */
 
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
-#include <asm/sizes.h>
-#include <linux/stringify.h>
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
 
 /*
  * High Level Configuration Options
  */
-#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20			/* in a NVidia Tegra20 core */
-#define CONFIG_TEGRA			/* which is a Tegra generic machine */
-#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+#define CONFIG_TEGRA20			/* NVidia Tegra20 core */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-#include <asm/arch/tegra.h>		/* get chip and board defs */
-
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
 /*
- * Display CPU and Board information
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
+#define CONFIG_STACKBASE	0x2800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
  */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_TEXT_BASE	0x0010E000
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x00108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
+#define CONFIG_SPL_STACK		0x000ffffc
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
 
-#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
 
 #ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR			0x1C406000
@@ -60,41 +64,6 @@ 
 #define TEGRA_LP0_VEC
 #endif
 
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
-
-/*
- * PllX Configuration
- */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX	1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
 /*
  * This parameter affects a TXFILLTUNING field that controls how much data is
  * sent to the latency fifo before it is sent to the wire. Without this
@@ -108,102 +77,10 @@ 
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS	4
 
-/* include default commands */
-#include <config_cmd_default.h>
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-/* remove unused commands */
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS		/* NFS support */
-#undef CONFIG_CMD_NET		/* network support */
-
-/* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
-#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		V_PROMPT
-/*
- * Increasing the size of the IO buffer as default nfsargs size is more
- *  than 256 and so it is not possible to edit it
- */
-#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
-
-#define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
-#define CONFIG_SYS_HZ			1000
-
-#define CONFIG_STACKBASE	0x2800000	/* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1
-#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
-
-#define CONFIG_SYS_TEXT_BASE	0x0010c000
-#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
-
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* 256M */
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_TEGRA_GPIO
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE		0x00108000
-#define CONFIG_SPL_MAX_SIZE		(CONFIG_SYS_TEXT_BASE - \
-						CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
-#define CONFIG_SPL_STACK		0x000ffffc
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"
-
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
-#endif /* __TEGRA20_COMMON_H */
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
new file mode 100644
index 0000000..c1ddcf3
--- /dev/null
+++ b/include/configs/tegra30-common.h
@@ -0,0 +1,54 @@ 
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra30/u-boot-spl.lds"
+
+#endif /* _TEGRA30_COMMON_H_ */