From patchwork Mon Dec 3 22:08:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Roth X-Patchwork-Id: 203489 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C57752C008D for ; Tue, 4 Dec 2012 10:29:31 +1100 (EST) Received: from localhost ([::1]:48232 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TfeJG-0008Qk-1X for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2012 17:16:18 -0500 Received: from eggs.gnu.org ([208.118.235.92]:50095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TfeIk-0007f3-8o for qemu-devel@nongnu.org; Mon, 03 Dec 2012 17:15:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TfeIj-00036q-0R for qemu-devel@nongnu.org; Mon, 03 Dec 2012 17:15:46 -0500 Received: from mail-ie0-f173.google.com ([209.85.223.173]:43922) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TfeIf-0002tM-F1; Mon, 03 Dec 2012 17:15:41 -0500 Received: by mail-ie0-f173.google.com with SMTP id e13so4875430iej.4 for ; Mon, 03 Dec 2012 14:15:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=lFsGfnYhHqeHy9y1vnffCQXvEicTiRaa8Puz6ujDNaU=; b=A9/qeIFANInlzJ1Yr8oHu8euNJses1x5oK/ZHkDXOMm8MbB8o6/Y1wjFzijpXmoo81 KCpYMntyMhtaxED9AFbb8iCL5iSWyx3e3fDJDdPqO/hQMXz/ip98fnaPPAhiQ+gO/xRf pIEDt3Jb0Lj3P1mxaB1wyJKrHCD1D7yVQUqBjiCbdr4ywee18x6Edx+oyj1FjsCWZLdL Br5+JXUxxzVpvQPsIABFQqpHaFkqwbpgfiLRkwLpBGl+HmbM66VI99GcbTZIgkwZaoiE G0bdIvDth7TO89hLBaVrXnvmsoXv7gV5FbT2nRG8bxAJQkiSffikQgRbcho/oI1GTwuH 4f8Q== Received: by 10.50.194.196 with SMTP id hy4mr549931igc.52.1354572941130; Mon, 03 Dec 2012 14:15:41 -0800 (PST) Received: from localhost ([32.97.110.59]) by mx.google.com with ESMTPS id yf6sm8875440igb.0.2012.12.03.14.15.40 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 03 Dec 2012 14:15:40 -0800 (PST) From: Michael Roth To: qemu-stable@nongnu.org Date: Mon, 3 Dec 2012 16:08:44 -0600 Message-Id: <1354572547-21271-21-git-send-email-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354572547-21271-1-git-send-email-mdroth@linux.vnet.ibm.com> References: <1354572547-21271-1-git-send-email-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.223.173 Cc: aliguori@us.ibm.com, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 20/43] mips/malta: fix CBUS UART interrupt pin X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Aurelien Jarno According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno (cherry picked from commit 68d001928b151a0c50f367c0bdca645b3d5e9ed3) Signed-off-by: Michael Roth --- hw/mips_malta.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index ad23f26..9289a28 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -860,7 +860,8 @@ void mips_malta_init (ram_addr_t ram_size, be = 0; #endif /* FPGA */ - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]); + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx);