Patchwork [21/43] target-mips: fix wrong microMIPS opcode encoding

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Submitter Michael Roth
Date Dec. 3, 2012, 10:08 p.m.
Message ID <1354572547-21271-22-git-send-email-mdroth@linux.vnet.ibm.com>
Download mbox | patch
Permalink /patch/203458/
State New
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Comments

Michael Roth - Dec. 3, 2012, 10:08 p.m.
From: "陳韋任 (Wei-Ren Chen)" <chenwj@iis.sinica.edu.tw>

While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 6801038bc52d61f81ac8a25fbe392f1bad982887)

Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
 target-mips/translate.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4e04e97..49907bb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9486,7 +9486,7 @@  enum {
 
     /* bits 13..12 for 0x32 */
     MULT_ACC = 0x0,
-    MULTU_ACC = 0x0,
+    MULTU_ACC = 0x1,
 
     /* bits 15..12 for 0x2c */
     SEB = 0x2,