From patchwork Sun Dec 2 14:49:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot, v2, 08/15] x86: Clean up MTRR 7 right before jumping to the kernel From: Simon Glass X-Patchwork-Id: 203226 X-Patchwork-Delegate: sjg@chromium.org Message-Id: <1354459800-22370-9-git-send-email-sjg@chromium.org> To: U-Boot Mailing List Cc: Stefan Reinauer Date: Sun, 2 Dec 2012 06:49:53 -0800 From: Stefan Reinauer This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- Changes in v2: - Use en/disable_caches() instead of en/disable_cache() - Use functions from Graeme's msr patch arch/x86/cpu/coreboot/coreboot.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index b942a3e..f262800 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include #include @@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis) void setup_pcat_compatibility() { } + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +int board_final_cleanup(void) +{ + /* Un-cache the ROM so the kernel has one + * more MTRR available. + */ + disable_caches(); + wrmsrl(MTRRphysBase_MSR(7), 0); + wrmsrl(MTRRphysMask_MSR(7), 0); + enable_caches(); + + return 0; +}