From patchwork Sun Dec 2 14:49:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 203226 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DBC882C007D for ; Mon, 3 Dec 2012 01:51:20 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E92104A047; Sun, 2 Dec 2012 15:51:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aE7Prsl4qDDt; Sun, 2 Dec 2012 15:51:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1515E4A048; Sun, 2 Dec 2012 15:51:05 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 564014A030 for ; Sun, 2 Dec 2012 15:51:01 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TW9r3VONwCBg for ; Sun, 2 Dec 2012 15:50:59 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ea0-f202.google.com (mail-ea0-f202.google.com [209.85.215.202]) by theia.denx.de (Postfix) with ESMTPS id 63E094A02E for ; Sun, 2 Dec 2012 15:50:57 +0100 (CET) Received: by mail-ea0-f202.google.com with SMTP id j12so261043eaa.3 for ; Sun, 02 Dec 2012 06:50:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=gGtF037CNS3nBxQjKJXmRNO9P7NTC1wh35pf+Iniq48=; b=ALCiR7JvgrmpHLW3q+sNHrAt0mynk+EWHylu5CeD/0Mw+TzKv33igXugvxQjvBBWFO X3wPv/zk9oGh47ZnzCis/juEVYxTlPn6jvWNPSvbBHn6lYZDZm9IhnTklaaNLTe0UZWe BHJjDSmA1/X36anxLQ9fPHyQlYNx/U+wGw0b+JI3qjQRxbQvMo5E4Yj3Ckvc3zwH7TSa 8BBNC55nPoRlKh9qE2XlLtBEuN3V3bBRnvSQu0TVGA9IoflbRKECWgNbNz6ERK/YZOzv FClf4qugqrXif8laAYNqwF+JXNZjm+x/zjmR7p9xb8JFaRi13rO953RZIJCSSJLhypqU grbg== Received: by 10.14.178.3 with SMTP id e3mr6059745eem.5.1354459857239; Sun, 02 Dec 2012 06:50:57 -0800 (PST) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id z47si2539313eel.0.2012.12.02.06.50.57 (version=TLSv1/SSLv3 cipher=AES128-SHA); Sun, 02 Dec 2012 06:50:57 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id D95AF20004E; Sun, 2 Dec 2012 06:50:56 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 483BD1610BE; Sun, 2 Dec 2012 06:50:56 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Sun, 2 Dec 2012 06:49:53 -0800 Message-Id: <1354459800-22370-9-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1354459800-22370-6-git-send-email-sjg@chromium.org> References: <1354459800-22370-6-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQn/CoYAs2/SuckJ9/FjEru9gO6l3Wk5Gx3kPkzXbf6cpQjPR40+ahn68CqybOd9mLG5OQ5X50ruatIov0iFvGHwdYIiRb+8c8L9HerSYRNa6romWJ1Kj8djT8tAGOcDqSMRu83UREQsSAO6mzcXE3Tj+vFa0lC19e+YyeKB87Uy0+Oo4ehEbFM6eg/AmbTWDn5U1icg Cc: Stefan Reinauer Subject: [U-Boot] [PATCH v2 08/15] x86: Clean up MTRR 7 right before jumping to the kernel X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Stefan Reinauer This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- Changes in v2: - Use en/disable_caches() instead of en/disable_cache() - Use functions from Graeme's msr patch arch/x86/cpu/coreboot/coreboot.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index b942a3e..f262800 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include #include @@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis) void setup_pcat_compatibility() { } + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +int board_final_cleanup(void) +{ + /* Un-cache the ROM so the kernel has one + * more MTRR available. + */ + disable_caches(); + wrmsrl(MTRRphysBase_MSR(7), 0); + wrmsrl(MTRRphysMask_MSR(7), 0); + enable_caches(); + + return 0; +}