Patchwork [U-Boot,v2,08/15] x86: Clean up MTRR 7 right before jumping to the kernel

login
register
mail settings
Submitter Simon Glass
Date Dec. 2, 2012, 2:49 p.m.
Message ID <1354459800-22370-9-git-send-email-sjg@chromium.org>
Download mbox | patch
Permalink /patch/203226/
State Accepted, archived
Delegated to: Simon Glass
Headers show

Comments

Simon Glass - Dec. 2, 2012, 2:49 p.m.
From: Stefan Reinauer <reinauer@chromium.org>

This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Use en/disable_caches() instead of en/disable_cache()
- Use functions from Graeme's msr patch

 arch/x86/cpu/coreboot/coreboot.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index b942a3e..f262800 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -26,6 +26,8 @@ 
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <asm/msr.h>
+#include <asm/cache.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
 #include <asm/arch/timestamp.h>
@@ -89,3 +91,19 @@  int board_eth_init(bd_t *bis)
 void setup_pcat_compatibility()
 {
 }
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+int board_final_cleanup(void)
+{
+	/* Un-cache the ROM so the kernel has one
+	 * more MTRR available.
+	 */
+	disable_caches();
+	wrmsrl(MTRRphysBase_MSR(7), 0);
+	wrmsrl(MTRRphysMask_MSR(7), 0);
+	enable_caches();
+
+	return 0;
+}