From patchwork Sun Dec 2 13:44:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 203207 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CD9342C00A7 for ; Mon, 3 Dec 2012 00:45:09 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A27A14A023; Sun, 2 Dec 2012 14:45:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id F9ik1lPnJzNi; Sun, 2 Dec 2012 14:45:06 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C09F04A026; Sun, 2 Dec 2012 14:45:01 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F26EE4A026 for ; Sun, 2 Dec 2012 14:44:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RbGXA4vBcuxi for ; Sun, 2 Dec 2012 14:44:57 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gg0-f202.google.com (mail-gg0-f202.google.com [209.85.161.202]) by theia.denx.de (Postfix) with ESMTPS id B32CC4A023 for ; Sun, 2 Dec 2012 14:44:56 +0100 (CET) Received: by mail-gg0-f202.google.com with SMTP id k1so290930ggn.3 for ; Sun, 02 Dec 2012 05:44:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=BChP0AFHcwKI8I3I5RTIghZ1h7yjil7LxkAM5L2d1Yc=; b=iY6bVnJn+n3K+DgtW14viCCVLaSilkuodXDTP5S+jEy01nt8h/2ZZruTRHzTpJHLqQ JEgco6yaD+q+xEv+dpdlFJWv344EHpBZDVcNbJKTmOrr5vnYaNaNqQ7tMVpcNM7IF2ob luqNfy9e0M9o+PaVvLLNAL9xXRla0Zepi6lbM3IYEFJw8DHhjKc9SxlRUlesuSBz1K+w bGYJtAymCG1mjLcsao4l1ou5q9rMO65+PV/Daine3/eI9gqfxDgh2Tfo/nBLUCiu8OCZ 3g266QeliK798Iy8k8Eqg4sBTt62tGZr9HkGV+gC+zpu7bcZGegyKYQ183S8K3HAx9gu jQ3w== Received: by 10.100.83.14 with SMTP id g14mr1214396anb.22.1354455894730; Sun, 02 Dec 2012 05:44:54 -0800 (PST) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id l20si678546yhi.2.2012.12.02.05.44.54 (version=TLSv1/SSLv3 cipher=AES128-SHA); Sun, 02 Dec 2012 05:44:54 -0800 (PST) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 9E8A082004A; Sun, 2 Dec 2012 05:44:54 -0800 (PST) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 4002E16110E; Sun, 2 Dec 2012 05:44:54 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Sun, 2 Dec 2012 05:44:44 -0800 Message-Id: <1354455885-9061-2-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 X-Gm-Message-State: ALoCoQlOsNvUXKsoEZy347oF2bHZTg9/SABTSMlqSl+fayRpWSMGX7aMkYNc/1g1yOMgoIfx5DTtNcxeDFAi4mv/I7s1836KCKlmcXjKNYi0b1y+G8ffGzdehcAP5asCpqHUJpmQfcMMWh4QlaWcCLc8fyNKmGu9WC69pIxjL3grwkcnBS78rbZl8MRkzv6HvJcUdA6Of7Cr Cc: Tom Rini Subject: [U-Boot] [PATCH v2 2/3] x86: Enable ICH6 GPIO controller for coreboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass --- Changes in v2: - Enable gpio command for coreboot also include/configs/coreboot.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index a010adc..fcfa7ed 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -138,6 +138,9 @@ #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE +/* x86 GPIOs are accessed through a PCI device */ +#define CONFIG_INTEL_ICH6_GPIO + /*----------------------------------------------------------------------- * Command line configuration. */ @@ -150,6 +153,7 @@ #define CONFIG_CMD_ECHO #undef CONFIG_CMD_FLASH #define CONFIG_CMD_FPGA +#define CONFIG_CMD_GPIO #define CONFIG_CMD_IMI #undef CONFIG_CMD_IMLS #define CONFIG_CMD_IRQ