Patchwork [2/3] hw/arm_gic: Fix comparison with priority mask register

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Submitter Peter Maydell
Date Nov. 29, 2012, 5:02 p.m.
Message ID <1354208577-8935-3-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/202793/
State New
Headers show

Comments

Peter Maydell - Nov. 29, 2012, 5:02 p.m.
The GIC spec states that only interrupts with higher priority
than the value in the GICC_PMR priority mask register are
passed through to the processor. We were incorrectly allowing
through interrupts with a priority equal to the specified
value: correct the comparison operation to match the spec.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm_gic.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Christoffer Dall - Dec. 1, 2012, 3:50 p.m.
On Thu, Nov 29, 2012 at 12:02 PM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> The GIC spec states that only interrupts with higher priority
> than the value in the GICC_PMR priority mask register are
> passed through to the processor. We were incorrectly allowing
> through interrupts with a priority equal to the specified
> value: correct the comparison operation to match the spec.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  hw/arm_gic.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index f9e423f..672d539 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -73,7 +73,7 @@ void gic_update(GICState *s)
>              }
>          }
>          level = 0;
> -        if (best_prio <= s->priority_mask[cpu]) {
> +        if (best_prio < s->priority_mask[cpu]) {
>              s->current_pending[cpu] = best_irq;
>              if (best_prio < s->running_priority[cpu]) {
>                  DPRINTF("Raised pending IRQ %d\n", best_irq);
> --
> 1.7.9.5
>
looks good to me
Igor Mitsyanko - Dec. 1, 2012, 9:27 p.m.
On 11/29/2012 9:02 PM, Peter Maydell wrote:
> The GIC spec states that only interrupts with higher priority
> than the value in the GICC_PMR priority mask register are
> passed through to the processor. We were incorrectly allowing
> through interrupts with a priority equal to the specified
> value: correct the comparison operation to match the spec.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   hw/arm_gic.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index f9e423f..672d539 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -73,7 +73,7 @@ void gic_update(GICState *s)
>               }
>           }
>           level = 0;
> -        if (best_prio <= s->priority_mask[cpu]) {
> +        if (best_prio < s->priority_mask[cpu]) {
>               s->current_pending[cpu] = best_irq;
>               if (best_prio < s->running_priority[cpu]) {
>                   DPRINTF("Raised pending IRQ %d\n", best_irq);
>


Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>

Patch

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index f9e423f..672d539 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -73,7 +73,7 @@  void gic_update(GICState *s)
             }
         }
         level = 0;
-        if (best_prio <= s->priority_mask[cpu]) {
+        if (best_prio < s->priority_mask[cpu]) {
             s->current_pending[cpu] = best_irq;
             if (best_prio < s->running_priority[cpu]) {
                 DPRINTF("Raised pending IRQ %d\n", best_irq);