Patchwork [3/3] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs

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Submitter Peter Maydell
Date Nov. 29, 2012, 5:02 p.m.
Message ID <1354208577-8935-4-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/202785/
State New
Headers show

Comments

Peter Maydell - Nov. 29, 2012, 5:02 p.m.
The GIC architecture specification for v1 and v2 GICs (as found
on the Cortex-A9 and newer) states that the GICC_PMR reset value
is zero; this differs from the 0xf0 reset value used on 11MPCore.
The NVIC is different again in not having a CPU interface; since
we share the GIC code we must force the priority mask field to
allow through all interrupts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm_gic_common.c |    6 +++++-
 hw/armv7m_nvic.c    |    4 +++-
 2 files changed, 8 insertions(+), 2 deletions(-)
Igor Mitsyanko - Dec. 1, 2012, 9:27 p.m.
On 11/29/2012 9:02 PM, Peter Maydell wrote:
> The GIC architecture specification for v1 and v2 GICs (as found
> on the Cortex-A9 and newer) states that the GICC_PMR reset value
> is zero; this differs from the 0xf0 reset value used on 11MPCore.
> The NVIC is different again in not having a CPU interface; since
> we share the GIC code we must force the priority mask field to
> allow through all interrupts.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   hw/arm_gic_common.c |    6 +++++-
>   hw/armv7m_nvic.c    |    4 +++-
>   2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c
> index 8369309..73ae331 100644
> --- a/hw/arm_gic_common.c
> +++ b/hw/arm_gic_common.c
> @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev)
>       int i;
>       memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
>       for (i = 0 ; i < s->num_cpu; i++) {
> -        s->priority_mask[i] = 0xf0;
> +        if (s->revision == REV_11MPCORE) {
> +            s->priority_mask[i] = 0xf0;
> +        } else {
> +            s->priority_mask[i] = 0;
> +        }
>           s->current_pending[i] = 1023;
>           s->running_irq[i] = 1023;
>           s->running_priority[i] = 0x100;
> diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
> index f0a2e7b..4963678 100644
> --- a/hw/armv7m_nvic.c
> +++ b/hw/armv7m_nvic.c
> @@ -455,9 +455,11 @@ static void armv7m_nvic_reset(DeviceState *dev)
>       nc->parent_reset(dev);
>       /* Common GIC reset resets to disabled; the NVIC doesn't have
>        * per-CPU interfaces so mark our non-existent CPU interface
> -     * as enabled by default.
> +     * as enabled by default, and with a priority mask which allows
> +     * all interrupts through.
>        */
>       s->gic.cpu_enabled[0] = 1;
> +    s->gic.priority_mask[0] = 0x100;
>       /* The NVIC as a whole is always enabled. */
>       s->gic.enabled = 1;
>       systick_reset(s);
>

Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>

Patch

diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c
index 8369309..73ae331 100644
--- a/hw/arm_gic_common.c
+++ b/hw/arm_gic_common.c
@@ -127,7 +127,11 @@  static void arm_gic_common_reset(DeviceState *dev)
     int i;
     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
     for (i = 0 ; i < s->num_cpu; i++) {
-        s->priority_mask[i] = 0xf0;
+        if (s->revision == REV_11MPCORE) {
+            s->priority_mask[i] = 0xf0;
+        } else {
+            s->priority_mask[i] = 0;
+        }
         s->current_pending[i] = 1023;
         s->running_irq[i] = 1023;
         s->running_priority[i] = 0x100;
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index f0a2e7b..4963678 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -455,9 +455,11 @@  static void armv7m_nvic_reset(DeviceState *dev)
     nc->parent_reset(dev);
     /* Common GIC reset resets to disabled; the NVIC doesn't have
      * per-CPU interfaces so mark our non-existent CPU interface
-     * as enabled by default.
+     * as enabled by default, and with a priority mask which allows
+     * all interrupts through.
      */
     s->gic.cpu_enabled[0] = 1;
+    s->gic.priority_mask[0] = 0x100;
     /* The NVIC as a whole is always enabled. */
     s->gic.enabled = 1;
     systick_reset(s);