Patchwork [for-1.3] qemu-tech.texi: update implemented xtensa features list

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Submitter Max Filippov
Date Nov. 29, 2012, 3:53 p.m.
Message ID <1354204400-19424-1-git-send-email-jcmvbkbc@gmail.com>
Download mbox | patch
Permalink /patch/202771/
State New
Headers show

Comments

Max Filippov - Nov. 29, 2012, 3:53 p.m.
Debug option is available since QEMU-1.2; FP coprocessor and
coprocessor context is available since QEMU-1.3.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 qemu-tech.texi |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)
Anthony Liguori - Nov. 30, 2012, 4:16 p.m.
Max Filippov <jcmvbkbc@gmail.com> writes:

> Debug option is available since QEMU-1.2; FP coprocessor and
> coprocessor context is available since QEMU-1.3.
>
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Applied. Thanks.

Regards,

Anthony Liguori

> ---
>  qemu-tech.texi |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/qemu-tech.texi b/qemu-tech.texi
> index d73dda8..8aefa74 100644
> --- a/qemu-tech.texi
> +++ b/qemu-tech.texi
> @@ -262,16 +262,16 @@ Current QEMU limitations:
>  
>  @item Core Xtensa ISA emulation, including most options: code density,
>  loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,
> -MAC16, miscellaneous operations, boolean, multiprocessor synchronization,
> +MAC16, miscellaneous operations, boolean, FP coprocessor, coprocessor
> +context, debug, multiprocessor synchronization,
>  conditional store, exceptions, relocatable vectors, unaligned exception,
>  interrupts (including high priority and timer), hardware alignment,
>  region protection, region translation, MMU, windowed registers, thread
>  pointer, processor ID.
>  
> -@item Not implemented options: FP coprocessor, coprocessor context,
> -data/instruction cache (including cache prefetch and locking), XLMI,
> -processor interface, debug. Also options not covered by the core ISA
> -(e.g. FLIX, wide branches) are not implemented.
> +@item Not implemented options: data/instruction cache (including cache
> +prefetch and locking), XLMI, processor interface. Also options not
> +covered by the core ISA (e.g. FLIX, wide branches) are not implemented.
>  
>  @item Can run most Xtensa Linux binaries.
>  
> -- 
> 1.7.7.6

Patch

diff --git a/qemu-tech.texi b/qemu-tech.texi
index d73dda8..8aefa74 100644
--- a/qemu-tech.texi
+++ b/qemu-tech.texi
@@ -262,16 +262,16 @@  Current QEMU limitations:
 
 @item Core Xtensa ISA emulation, including most options: code density,
 loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,
-MAC16, miscellaneous operations, boolean, multiprocessor synchronization,
+MAC16, miscellaneous operations, boolean, FP coprocessor, coprocessor
+context, debug, multiprocessor synchronization,
 conditional store, exceptions, relocatable vectors, unaligned exception,
 interrupts (including high priority and timer), hardware alignment,
 region protection, region translation, MMU, windowed registers, thread
 pointer, processor ID.
 
-@item Not implemented options: FP coprocessor, coprocessor context,
-data/instruction cache (including cache prefetch and locking), XLMI,
-processor interface, debug. Also options not covered by the core ISA
-(e.g. FLIX, wide branches) are not implemented.
+@item Not implemented options: data/instruction cache (including cache
+prefetch and locking), XLMI, processor interface. Also options not
+covered by the core ISA (e.g. FLIX, wide branches) are not implemented.
 
 @item Can run most Xtensa Linux binaries.