Patchwork [U-Boot] EXYNOS: Add L2 Cache Support.

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Submitter Rajeshwari Birje
Date Nov. 29, 2012, 8:12 a.m.
Message ID <1354176776-17407-1-git-send-email-rajeshwari.s@samsung.com>
Download mbox | patch
Permalink /patch/202683/
State Superseded
Headers show

Comments

Rajeshwari Birje - Nov. 29, 2012, 8:12 a.m.
This patch set adds L2 Cache Support to EXYNOS.

Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
 arch/arm/cpu/armv7/exynos/soc.c |   36 ++++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
Kyungmin Park - Nov. 29, 2012, 2:42 p.m.
On Thu, Nov 29, 2012 at 5:12 PM, Rajeshwari Shinde
<rajeshwari.s@samsung.com> wrote:
> This patch set adds L2 Cache Support to EXYNOS.
>
> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
>  arch/arm/cpu/armv7/exynos/soc.c |   36 ++++++++++++++++++++++++++++++++++++
>  1 files changed, 36 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
> index ab65b8d..a45bbfb 100644
> --- a/arch/arm/cpu/armv7/exynos/soc.c
> +++ b/arch/arm/cpu/armv7/exynos/soc.c
> @@ -23,6 +23,14 @@
>
>  #include <common.h>
>  #include <asm/io.h>
> +#include <asm/system.h>
> +
> +enum l2_cache_params {
> +       CACHE_TAG_RAM_SETUP = (1<<9),
> +       CACHE_DATA_RAM_SETUP = (1<<5),
> +       CACHE_TAG_RAM_LATENCY = (2<<6),
> +       CACHE_DATA_RAM_LATENCY = (2<<0)
> +};
>
>  void reset_cpu(ulong addr)
>  {
> @@ -36,3 +44,31 @@ void enable_caches(void)
>         dcache_enable();
>  }
>  #endif
> +
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +/*
> + * Set L2 cache parameters
> + */
> +static void exynos5_set_l2cache_params(void)
> +{
> +       unsigned int val = 0;
> +
> +       asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
> +
> +       val |= CACHE_TAG_RAM_SETUP |
> +               CACHE_DATA_RAM_SETUP |
> +               CACHE_TAG_RAM_LATENCY |
> +               CACHE_DATA_RAM_LATENCY;
> +
> +       asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
> +}
> +
> +/*
> + * Sets L2 cache related parameters before enabling data cache
> + */
> +void v7_outer_cache_enable(void)
> +{
if (soc_is_exynos5250())
> +       exynos5_set_l2cache_params();
Since it's not working at exynos4

Thank you,
Kyungmin Park
> +}
> +#endif
> +
> --
> 1.7.4.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Rajeshwari Birje - Nov. 30, 2012, 4:05 a.m.
Hi Kyungmin Park,

Thank you for comment.
Will make the change and resubmit the patch.

Regards,
Rajeshwari Shinde.

On Thu, Nov 29, 2012 at 8:12 PM, Kyungmin Park <kmpark@infradead.org> wrote:
> On Thu, Nov 29, 2012 at 5:12 PM, Rajeshwari Shinde
> <rajeshwari.s@samsung.com> wrote:
>> This patch set adds L2 Cache Support to EXYNOS.
>>
>> Signed-off-by: Arun Mankuzhi <arun.m@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>>  arch/arm/cpu/armv7/exynos/soc.c |   36 ++++++++++++++++++++++++++++++++++++
>>  1 files changed, 36 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
>> index ab65b8d..a45bbfb 100644
>> --- a/arch/arm/cpu/armv7/exynos/soc.c
>> +++ b/arch/arm/cpu/armv7/exynos/soc.c
>> @@ -23,6 +23,14 @@
>>
>>  #include <common.h>
>>  #include <asm/io.h>
>> +#include <asm/system.h>
>> +
>> +enum l2_cache_params {
>> +       CACHE_TAG_RAM_SETUP = (1<<9),
>> +       CACHE_DATA_RAM_SETUP = (1<<5),
>> +       CACHE_TAG_RAM_LATENCY = (2<<6),
>> +       CACHE_DATA_RAM_LATENCY = (2<<0)
>> +};
>>
>>  void reset_cpu(ulong addr)
>>  {
>> @@ -36,3 +44,31 @@ void enable_caches(void)
>>         dcache_enable();
>>  }
>>  #endif
>> +
>> +#ifndef CONFIG_SYS_L2CACHE_OFF
>> +/*
>> + * Set L2 cache parameters
>> + */
>> +static void exynos5_set_l2cache_params(void)
>> +{
>> +       unsigned int val = 0;
>> +
>> +       asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
>> +
>> +       val |= CACHE_TAG_RAM_SETUP |
>> +               CACHE_DATA_RAM_SETUP |
>> +               CACHE_TAG_RAM_LATENCY |
>> +               CACHE_DATA_RAM_LATENCY;
>> +
>> +       asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
>> +}
>> +
>> +/*
>> + * Sets L2 cache related parameters before enabling data cache
>> + */
>> +void v7_outer_cache_enable(void)
>> +{
> if (soc_is_exynos5250())
>> +       exynos5_set_l2cache_params();
> Since it's not working at exynos4
>
> Thank you,
> Kyungmin Park
>> +}
>> +#endif
>> +
>> --
>> 1.7.4.4
>>
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Patch

diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index ab65b8d..a45bbfb 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -23,6 +23,14 @@ 
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/system.h>
+
+enum l2_cache_params {
+	CACHE_TAG_RAM_SETUP = (1<<9),
+	CACHE_DATA_RAM_SETUP = (1<<5),
+	CACHE_TAG_RAM_LATENCY = (2<<6),
+	CACHE_DATA_RAM_LATENCY = (2<<0)
+};
 
 void reset_cpu(ulong addr)
 {
@@ -36,3 +44,31 @@  void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+	unsigned int val = 0;
+
+	asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
+
+	val |= CACHE_TAG_RAM_SETUP |
+		CACHE_DATA_RAM_SETUP |
+		CACHE_TAG_RAM_LATENCY |
+		CACHE_DATA_RAM_LATENCY;
+
+	asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+	exynos5_set_l2cache_params();
+}
+#endif
+