From patchwork Tue Nov 27 08:59:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 202172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 781B62C0084 for ; Tue, 27 Nov 2012 21:14:45 +1100 (EST) Received: from localhost ([::1]:55074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdH2Q-0007ex-IW for incoming@patchwork.ozlabs.org; Tue, 27 Nov 2012 04:01:06 -0500 Received: from eggs.gnu.org ([208.118.235.92]:36004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdH14-0005l5-S0 for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TdH0v-0004zz-Ew for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:9984) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdH0v-0004za-6m for qemu-devel@nongnu.org; Tue, 27 Nov 2012 03:59:33 -0500 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qAR8xWbt003945 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 27 Nov 2012 03:59:32 -0500 Received: from rincewind.home.kraxel.org (ovpn-116-25.ams2.redhat.com [10.36.116.25]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id qAR8xVK9027684; Tue, 27 Nov 2012 03:59:31 -0500 Received: by rincewind.home.kraxel.org (Postfix, from userid 500) id 6C1A84090F; Tue, 27 Nov 2012 09:59:29 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Tue, 27 Nov 2012 09:59:16 +0100 Message-Id: <1354006768-13128-7-git-send-email-kraxel@redhat.com> In-Reply-To: <1354006768-13128-1-git-send-email-kraxel@redhat.com> References: <1354006768-13128-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: afaerber@suse.de, Gerd Hoffmann Subject: [Qemu-devel] [PATCH v2 06/18] apci: switch evt to memory api X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Gerd Hoffmann --- hw/acpi.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++-- hw/acpi.h | 6 ++++-- hw/acpi_ich9.c | 18 +----------------- hw/acpi_piix4.c | 18 +----------------- hw/vt82c686.c | 18 +----------------- 5 files changed, 54 insertions(+), 55 deletions(-) diff --git a/hw/acpi.c b/hw/acpi.c index 956db95..e58e45f 100644 --- a/hw/acpi.c +++ b/hw/acpi.c @@ -275,7 +275,7 @@ uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar) return ar->pm1.evt.sts; } -void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) +static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) { uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar); if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) { @@ -285,7 +285,7 @@ void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) ar->pm1.evt.sts &= ~val; } -void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val) +static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val) { ar->pm1.evt.en = val; qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, @@ -310,6 +310,51 @@ void acpi_pm1_evt_reset(ACPIREGS *ar) qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_PMTIMER, 0); } +static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width) +{ + ACPIREGS *ar = opaque; + switch (addr) { + case 0: + return acpi_pm1_evt_get_sts(ar); + case 2: + return ar->pm1.evt.en; + default: + return 0; + } +} + +static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + ACPIREGS *ar = opaque; + switch (addr) { + case 0: + acpi_pm1_evt_write_sts(ar, val); + ar->pm1.evt.update_sci(ar); + break; + case 2: + acpi_pm1_evt_write_en(ar, val); + ar->pm1.evt.update_sci(ar); + break; + } +} + +static const MemoryRegionOps acpi_pm_evt_ops = { + .read = acpi_pm_evt_read, + .write = acpi_pm_evt_write, + .valid.min_access_size = 2, + .valid.max_access_size = 2, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci, + MemoryRegion *parent) +{ + ar->pm1.evt.update_sci = update_sci; + memory_region_init_io(&ar->pm1.evt.io, &acpi_pm_evt_ops, ar, "acpi-evt", 4); + memory_region_add_subregion(parent, 0, &ar->pm1.evt.io); +} + /* ACPI PM_TMR */ void acpi_pm_tmr_update(ACPIREGS *ar, bool enable) { diff --git a/hw/acpi.h b/hw/acpi.h index 97aaab8..918d7f5 100644 --- a/hw/acpi.h +++ b/hw/acpi.h @@ -91,8 +91,10 @@ struct ACPIPMTimer { }; struct ACPIPM1EVT { + MemoryRegion io; uint16_t sts; uint16_t en; + acpi_update_sci_fn update_sci; }; struct ACPIPM1CNT { @@ -135,10 +137,10 @@ static inline int64_t acpi_pm_tmr_get_clock(void) /* PM1a_EVT: piix and ich9 don't implement PM1b. */ uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar); -void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val); -void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val); void acpi_pm1_evt_power_down(ACPIREGS *ar); void acpi_pm1_evt_reset(ACPIREGS *ar); +void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci, + MemoryRegion *parent); /* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent); diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c index 7b6c2ef..3b5bac6 100644 --- a/hw/acpi_ich9.c +++ b/hw/acpi_ich9.c @@ -105,17 +105,7 @@ static uint32_t pm_ioport_readb(void *opaque, uint32_t addr) static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { - ICH9LPCPMRegs *pm = opaque; - switch (addr & ICH9_PMIO_MASK) { - case ICH9_PMIO_PM1_STS: - acpi_pm1_evt_write_sts(&pm->acpi_regs, val); - pm_update_sci(pm); - break; - case ICH9_PMIO_PM1_EN: - pm->acpi_regs.pm1.evt.en = val; - pm_update_sci(pm); - break; default: pm_ioport_write_fallback(opaque, addr, 2, val); break; @@ -125,16 +115,9 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) { - ICH9LPCPMRegs *pm = opaque; uint32_t val; switch (addr & ICH9_PMIO_MASK) { - case ICH9_PMIO_PM1_STS: - val = acpi_pm1_evt_get_sts(&pm->acpi_regs); - break; - case ICH9_PMIO_PM1_EN: - val = pm->acpi_regs.pm1.evt.en; - break; default: val = pm_ioport_read_fallback(opaque, addr, 2); break; @@ -312,6 +295,7 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) memory_region_add_subregion(get_system_io(), 0, &pm->io); acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); + acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io); acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); acpi_gpe_blk(&pm->acpi_regs, ICH9_PMIO_GPE0_STS); diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 9d5e346..d4e28c4 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -113,22 +113,12 @@ static void pm_tmr_timer(ACPIREGS *ar) static void pm_ioport_write(void *opaque, hwaddr addr, uint64_t val, unsigned width) { - PIIX4PMState *s = opaque; - if (width != 2) { PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n", (unsigned)addr, width, (unsigned)val); } switch(addr) { - case 0x00: - acpi_pm1_evt_write_sts(&s->ar, val); - pm_update_sci(s); - break; - case 0x02: - acpi_pm1_evt_write_en(&s->ar, val); - pm_update_sci(s); - break; default: break; } @@ -138,16 +128,9 @@ static void pm_ioport_write(void *opaque, hwaddr addr, uint64_t val, static uint64_t pm_ioport_read(void *opaque, hwaddr addr, unsigned width) { - PIIX4PMState *s = opaque; uint32_t val; switch(addr) { - case 0x00: - val = acpi_pm1_evt_get_sts(&s->ar); - break; - case 0x02: - val = s->ar.pm1.evt.en; - break; default: val = 0; break; @@ -455,6 +438,7 @@ static int piix4_pm_initfn(PCIDevice *dev) memory_region_add_subregion(get_system_io(), 0, &s->io); acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); + acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_cnt_init(&s->ar, &s->io); acpi_gpe_init(&s->ar, GPE_LEN); diff --git a/hw/vt82c686.c b/hw/vt82c686.c index 15f0b6a..52f46f1 100644 --- a/hw/vt82c686.c +++ b/hw/vt82c686.c @@ -199,18 +199,8 @@ static void pm_tmr_timer(ACPIREGS *ar) static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) { - VT686PMState *s = opaque; - addr &= 0x0f; switch (addr) { - case 0x00: - acpi_pm1_evt_write_sts(&s->ar, val); - pm_update_sci(s); - break; - case 0x02: - acpi_pm1_evt_write_en(&s->ar, val); - pm_update_sci(s); - break; default: break; } @@ -219,17 +209,10 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) { - VT686PMState *s = opaque; uint32_t val; addr &= 0x0f; switch (addr) { - case 0x00: - val = acpi_pm1_evt_get_sts(&s->ar); - break; - case 0x02: - val = s->ar.pm1.evt.en; - break; default: val = 0; break; @@ -437,6 +420,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev) memory_region_add_subregion(get_system_io(), 0, &s->io); acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); + acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_cnt_init(&s->ar, &s->io); pm_smbus_init(&s->dev.qdev, &s->smb);