From patchwork Tue Nov 27 02:47:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [01/16] powerpc: Add new CPU feature bit for transactional memory From: Michael Neuling X-Patchwork-Id: 202070 Message-Id: <1353984488-1283-2-git-send-email-mikey@neuling.org> To: Benjamin Herrenschmidt Cc: Michael Neuling , linuxppc-dev@lists.ozlabs.org, Matt Evans Date: Tue, 27 Nov 2012 13:47:53 +1100 Signed-off-by: Matt Evans Signed-off-by: Michael Neuling --- arch/powerpc/include/asm/cputable.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index fc4d2c5..f2163da 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -171,6 +171,7 @@ extern const char *powerpc_base_platform; #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000) #define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000) #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x2000000000000000) +#define CPU_FTR_TM LONG_ASM_CONST(0x4000000000000000) #ifndef __ASSEMBLY__ @@ -216,6 +217,13 @@ extern const char *powerpc_base_platform; #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 #endif +/* We only set the TM feature if the kernel was compiled with TM supprt */ +#ifdef CONFIG_TRANSACTIONAL_MEM +#define CPU_FTR_TM_COMP CPU_FTR_TM +#else +#define CPU_FTR_TM_COMP 0 +#endif + /* We need to mark all pages as being coherent if we're SMP or we have a * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II * require it for PCI "streaming/prefetch" to work properly.