From patchwork Tue Nov 27 02:29:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Auld X-Patchwork-Id: 202069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1730B2C008E for ; Tue, 27 Nov 2012 13:30:01 +1100 (EST) Received: from localhost ([::1]:60839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdAvu-00024p-W5 for incoming@patchwork.ozlabs.org; Mon, 26 Nov 2012 21:29:58 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdAvo-00024k-3G for qemu-devel@nongnu.org; Mon, 26 Nov 2012 21:29:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TdAvm-0005a3-C5 for qemu-devel@nongnu.org; Mon, 26 Nov 2012 21:29:52 -0500 Received: from mail-pa0-f67.google.com ([209.85.220.67]:54283) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TdAvl-0005Zx-UL for qemu-devel@nongnu.org; Mon, 26 Nov 2012 21:29:50 -0500 Received: by mail-pa0-f67.google.com with SMTP id fb11so5069076pad.10 for ; Mon, 26 Nov 2012 18:29:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=subject:from:reply-to:to:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=cCuFnm56v2p8jJWRu4Uty9dQ6UJpsrj0UTXF0uOWS8w=; b=BIOxLACncXV+RcKG6tE11Vd9ws0FVH4z4mpxvcCQ1hF3/TaAiLrbW7vXGVVSOu3WMu z0A5N4p7+pOxOnwqks3VTaYOPJ3crOmY8gfUUkGrdkPOOZ14aJiibQvScFW+QaqXWOVK AIr5oOrWbse5AAf3xsffMFMXu1PZ29a0ETWayk37B/gVGB8Gv3Lj0PGNiNxNyT8jxQxm sHFGyoIC9ETNCl/tjSYZ5lhi9DqBFmHxkMBYUFPvzHZNyF265+vgYa/TKYoZsJhB3Xja vUMhPg9Td6YHbsmg4adWwf2qWl30CCkwqNF4uDxNRbB5x6hMs/Pcr9PKRf2rXgnQNNhc /uLQ== Received: by 10.66.89.138 with SMTP id bo10mr1046647pab.1.1353983389057; Mon, 26 Nov 2012 18:29:49 -0800 (PST) Received: from [192.168.0.3] (c-24-20-151-104.hsd1.or.comcast.net. [24.20.151.104]) by mx.google.com with ESMTPS id x6sm9750034pav.29.2012.11.26.18.29.47 (version=SSLv3 cipher=OTHER); Mon, 26 Nov 2012 18:29:48 -0800 (PST) From: Will Auld To: qemu-devel , Gleb , "mtosatti@redhat.com" , "kvm@vger.kernel.org" , "donald.d.dugger@intel.com" , "jinsong.liu@intel.com" , "xiantao.zhang@intel.com" , "will.auld@intel.com" , "avi@redhat.com" Date: Mon, 26 Nov 2012 18:29:46 -0800 Message-ID: <1353983386.12838.1.camel@WillAuldHomeLinux> Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 (2.28.3-24.el6) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.67 Subject: [Qemu-devel] [PATCH V4] target-i386: Enabling IA32_TSC_ADJUST for Qemu KVM guest VMs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list Reply-To: will.auld@intel.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported Basic design is to emulate the MSR by allowing reads and writes to the hypervisor vcpu specific locations to store the value of the emulated MSRs. In this way the IA32_TSC_ADJUST value will be included in all reads to the TSC MSR whether through rdmsr or rdtsc. As this is a new MSR that the guest may access and modify its value needs to be migrated along with the other MRSs. The changes here are specifically for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added for migrating its value. Signed-off-by: Will Auld --- target-i386/cpu.h | 2 ++ target-i386/kvm.c | 14 ++++++++++++++ target-i386/machine.c | 21 +++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index aabf993..9dedaa6 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -284,6 +284,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe @@ -701,6 +702,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_adjust; uint64_t tsc_deadline; uint64_t mcg_status; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 696b14a..6d2a061 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -61,6 +61,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool has_msr_star; static bool has_msr_hsave_pa; +static bool has_msr_tsc_adjust; static bool has_msr_tsc_deadline; static bool has_msr_async_pf_en; static bool has_msr_misc_enable; @@ -641,6 +642,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hsave_pa = true; continue; } + if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) { + has_msr_tsc_adjust = true; + continue; + } if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) { has_msr_tsc_deadline = true; continue; @@ -978,6 +983,9 @@ static int kvm_put_msrs(CPUX86State *env, int level) if (has_msr_hsave_pa) { kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); } + if (has_msr_tsc_adjust) { + kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); + } if (has_msr_tsc_deadline) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); } @@ -1234,6 +1242,9 @@ static int kvm_get_msrs(CPUX86State *env) if (has_msr_hsave_pa) { msrs[n++].index = MSR_VM_HSAVE_PA; } + if (has_msr_tsc_adjust) { + msrs[n++].index = MSR_TSC_ADJUST; + } if (has_msr_tsc_deadline) { msrs[n++].index = MSR_IA32_TSCDEADLINE; } @@ -1308,6 +1319,9 @@ static int kvm_get_msrs(CPUX86State *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; + case MSR_TSC_ADJUST: + env->tsc_adjust = msrs[i].data; + break; case MSR_IA32_TSCDEADLINE: env->tsc_deadline = msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index a8be058..df3f779 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -310,6 +310,24 @@ static const VMStateDescription vmstate_fpop_ip_dp = { } }; +static bool tsc_adjust_needed(void *opaque) +{ + CPUX86State *env = opaque; + + return env->tsc_adjust != 0; +} + +static const VMStateDescription vmstate_msr_tsc_adjust = { + .name = "cpu/msr_tsc_adjust", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField []) { + VMSTATE_UINT64(tsc_adjust, CPUX86State), + VMSTATE_END_OF_LIST() + } +}; + static bool tscdeadline_needed(void *opaque) { CPUX86State *env = opaque; @@ -457,6 +475,9 @@ static const VMStateDescription vmstate_cpu = { .vmsd = &vmstate_fpop_ip_dp, .needed = fpop_ip_dp_needed, }, { + .vmsd = &vmstate_msr_tsc_adjust, + .needed = tsc_adjust_needed, + }, { .vmsd = &vmstate_msr_tscdeadline, .needed = tscdeadline_needed, }, {