From patchwork Mon Nov 26 15:13:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 201872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D1342C0085 for ; Tue, 27 Nov 2012 04:11:28 +1100 (EST) Received: from localhost ([::1]:41538 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Td2DO-0001O0-B7 for incoming@patchwork.ozlabs.org; Mon, 26 Nov 2012 12:11:26 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Td0Mx-0003xv-35 for qemu-devel@nongnu.org; Mon, 26 Nov 2012 10:13:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Td0Mn-0006LD-Ej for qemu-devel@nongnu.org; Mon, 26 Nov 2012 10:13:10 -0500 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:44224 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Td0Mn-0006Kt-7l for qemu-devel@nongnu.org; Mon, 26 Nov 2012 10:13:01 -0500 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id DB0F625B654 for ; Mon, 26 Nov 2012 16:12:57 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Mon, 26 Nov 2012 16:13:21 +0100 Message-Id: <1353942801-24441-1-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.5.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 X-Mailman-Approved-At: Mon, 26 Nov 2012 12:11:14 -0500 Cc: petarj@mips.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic Reviewed-by: Eric Johnson --- target-mips/dsp_helper.c | 2 +- tests/tcg/mips/mips32-dsp/insv.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e7949c2..fda5f04 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ \ filter = ((int32_t)0x01 << size) - 1; \ filter = filter << pos; \ - temprs = rs & filter; \ + temprs = (rs << pos) & filter; \ temprt = rt & ~filter; \ temp = temprs | temprt; \ \ diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c index 7e3b047..243b007 100644 --- a/tests/tcg/mips/mips32-dsp/insv.c +++ b/tests/tcg/mips/mips32-dsp/insv.c @@ -10,7 +10,7 @@ int main() dsp = 0x305; rt = 0x12345678; rs = 0x87654321; - result = 0x12345338; + result = 0x12345438; __asm ("wrdsp %2, 0x03\n\t" "insv %0, %1\n\t"