Patchwork [U-Boot] mx23: Add POWER and CLKCTRL register definitions

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Submitter Marek Vasut
Date Nov. 25, 2012, 12:21 a.m.
Message ID <1353802869-19200-1-git-send-email-marex@denx.de>
Download mbox | patch
Permalink /patch/201495/
State Deferred
Delegated to: Stefano Babic
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Comments

Marek Vasut - Nov. 25, 2012, 12:21 a.m.
Add register definitions for the i.MX23 power control block and
clock control block. These are essential for the basic bootstrap
of the i.MX23. Also, properly include them in imx-regs.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mxs/imx-regs.h          |    5 +
 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h |  221 +++++++++++++
 arch/arm/include/asm/arch-mxs/regs-power-mx23.h   |  357 +++++++++++++++++++++
 3 files changed, 583 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
 create mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
Otavio Salvador - Nov. 25, 2012, 2:52 a.m.
On Sat, Nov 24, 2012 at 10:21 PM, Marek Vasut <marex@denx.de> wrote:
> Add register definitions for the i.MX23 power control block and
> clock control block. These are essential for the basic bootstrap
> of the i.MX23. Also, properly include them in imx-regs.h .
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>

Please don't merge it now as this has been already done in my branch with mx23.
Marek Vasut - Nov. 25, 2012, 2:54 a.m.
Dear Otavio Salvador,

> On Sat, Nov 24, 2012 at 10:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Add register definitions for the i.MX23 power control block and
> > clock control block. These are essential for the basic bootstrap
> > of the i.MX23. Also, properly include them in imx-regs.h .
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> 
> Please don't merge it now as this has been already done in my branch with
> mx23.

I'm attaching a proper diff against your branch. There are multiple wrong and 
missing bits in your branch. This patch is done by processing the FSL-provided 
header file and cross-checking with the datasheet.

So, this patch is right, yours is wrong. Sorry.

--- arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h   2012-10-01 
02:46:18.000000000 +0200
+++ ../u-boot-imx/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h     
2012-11-25 00:55:43.299072391 +0100
@@ -1,8 +1,11 @@
 /*
  * Freescale i.MX23 CLKCTRL Register Definitions
  *
- * Copyright (C) 2012 Otavio Salvador <otavio@ossystems.com.br>
- * on behalf of O.S. Systems Software LTDA.
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,7 +31,8 @@
 #ifndef        __ASSEMBLY__
 struct mxs_clkctrl_regs {
        mxs_reg_32(hw_clkctrl_pll0ctrl0)        /* 0x00 */
-       mxs_reg_32(hw_clkctrl_pll0ctrl1)        /* 0x10 */
+       uint32_t        hw_clkctrl_pll0ctrl1;   /* 0x10 */
+       uint32_t        reserved_pll0ctrl1[3];  /* 0x14-0x1c */
        mxs_reg_32(hw_clkctrl_cpu)              /* 0x20 */
        mxs_reg_32(hw_clkctrl_hbus)             /* 0x30 */
        mxs_reg_32(hw_clkctrl_xbus)             /* 0x40 */
@@ -39,15 +43,13 @@
        mxs_reg_32(hw_clkctrl_spdif)            /* 0x90 */
        mxs_reg_32(hw_clkctrl_emi)              /* 0xa0 */
 
-       uint32_t reserved[4];
-
-       mxs_reg_32(hw_clkctrl_saif)             /* 0x0c0 */
-       mxs_reg_32(hw_clkctrl_tv)               /* 0x0d0 */
-       mxs_reg_32(hw_clkctrl_etm)              /* 0x0e0 */
-
-       mxs_reg_8(hw_clkctrl_frac0)     /* 0x0f0 */
-       mxs_reg_8(hw_clkctrl_frac1)     /* 0x100 */
+       uint32_t        reserved1[4];
 
+       mxs_reg_32(hw_clkctrl_saif0)            /* 0xc0 */
+       mxs_reg_32(hw_clkctrl_tv)               /* 0xd0 */
+       mxs_reg_32(hw_clkctrl_etm)              /* 0xe0 */
+       mxs_reg_8(hw_clkctrl_frac0)             /* 0xf0 */
+       mxs_reg_8(hw_clkctrl_frac1)             /* 0x100 */
        mxs_reg_32(hw_clkctrl_clkseq)           /* 0x110 */
        mxs_reg_32(hw_clkctrl_reset)            /* 0x120 */
        mxs_reg_32(hw_clkctrl_status)           /* 0x130 */
@@ -87,11 +89,11 @@
 #define        CLKCTRL_CPU_DIV_XTAL_MASK               (0x3ff << 16)
 #define        CLKCTRL_CPU_DIV_XTAL_OFFSET             16
 #define        CLKCTRL_CPU_INTERRUPT_WAIT              (1 << 12)
-#define        CLKCTRL_CPU_DIV_CPU_FRAC_EN             (1 << 5)
+#define        CLKCTRL_CPU_DIV_CPU_FRAC_EN             (1 << 10)
 #define        CLKCTRL_CPU_DIV_CPU_MASK                0x3f
 #define        CLKCTRL_CPU_DIV_CPU_OFFSET              0
 
-#define        CLKCTRL_HBUS_ASM_BUSY                   (1 << 29)
+#define        CLKCTRL_HBUS_BUSY                       (1 << 29)
 #define        CLKCTRL_HBUS_DCP_AS_ENABLE              (1 << 28)
 #define        CLKCTRL_HBUS_PXP_AS_ENABLE              (1 << 27)
 #define        CLKCTRL_HBUS_APBHDMA_AS_ENABLE          (1 << 26)
@@ -101,7 +103,7 @@
 #define        CLKCTRL_HBUS_CPU_DATA_AS_ENABLE         (1 << 22)
 #define        CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE        (1 << 21)
 #define        CLKCTRL_HBUS_AUTO_SLOW_MODE             (1 << 20)
-#define        CLKCTRL_HBUS_SLOW_DIV_MASK              (0x7 << 18)
+#define        CLKCTRL_HBUS_SLOW_DIV_MASK              (0x7 << 16)
 #define        CLKCTRL_HBUS_SLOW_DIV_OFFSET            16
 #define        CLKCTRL_HBUS_SLOW_DIV_BY1               (0x0 << 16)
 #define        CLKCTRL_HBUS_SLOW_DIV_BY2               (0x1 << 16)
@@ -114,16 +116,25 @@
 #define        CLKCTRL_HBUS_DIV_OFFSET                 0
 
 #define        CLKCTRL_XBUS_BUSY                       (1 << 31)
-#define        CLKCTRL_XBUS_DIV_FRAC_EN                (1 << 9)
+#define        CLKCTRL_XBUS_DIV_FRAC_EN                (1 << 10)
 #define        CLKCTRL_XBUS_DIV_MASK                   0x3ff
 #define        CLKCTRL_XBUS_DIV_OFFSET                 0
 
 #define        CLKCTRL_XTAL_UART_CLK_GATE              (1 << 31)
+#define        CLKCTRL_XTAL_FILT_CLK24M_GATE           (1 << 30)
 #define        CLKCTRL_XTAL_PWM_CLK24M_GATE            (1 << 29)
+#define        CLKCTRL_XTAL_DRI_CLK24M_GATE            (1 << 28)
+#define        CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE         (1 << 27)
 #define        CLKCTRL_XTAL_TIMROT_CLK32K_GATE         (1 << 26)
 #define        CLKCTRL_XTAL_DIV_UART_MASK              0x3
 #define        CLKCTRL_XTAL_DIV_UART_OFFSET            0
 
+#define        CLKCTRL_PIX_CLKGATE                     (1 << 31)
+#define        CLKCTRL_PIX_BUSY                        (1 << 29)
+#define        CLKCTRL_PIX_DIV_FRAC_EN                 (1 << 12)
+#define        CLKCTRL_PIX_DIV_MASK                    0xfff
+#define        CLKCTRL_PIX_DIV_OFFSET                  0
+
 #define        CLKCTRL_SSP_CLKGATE                     (1 << 31)
 #define        CLKCTRL_SSP_BUSY                        (1 << 29)
 #define        CLKCTRL_SSP_DIV_FRAC_EN                 (1 << 9)
@@ -151,11 +162,23 @@
 #define        CLKCTRL_EMI_DIV_EMI_MASK                0x3f
 #define        CLKCTRL_EMI_DIV_EMI_OFFSET              0
 
-#define        CLKCTRL_SAIF_CLKGATE                    (1 << 31)
-#define        CLKCTRL_SAIF_BUSY                       (1 << 29)
-#define        CLKCTRL_SAIF_DIV_FRAC_EN                (1 << 16)
-#define        CLKCTRL_SAIF_DIV_MASK                   0xffff
-#define        CLKCTRL_SAIF_DIV_OFFSET         0
+#define        CLKCTRL_IR_CLKGATE                      (1 << 31)
+#define        CLKCTRL_IR_AUTO_DIV                     (1 << 29)
+#define        CLKCTRL_IR_IR_BUSY                      (1 << 28)
+#define        CLKCTRL_IR_IROV_BUSY                    (1 << 27)
+#define        CLKCTRL_IR_IROV_DIV_MASK                (0x1ff << 16)
+#define        CLKCTRL_IR_IROV_DIV_OFFSET              16
+#define        CLKCTRL_IR_IR_DIV_MASK                  0x3ff
+#define        CLKCTRL_IR_IR_DIV_OFFSET                0
+
+#define        CLKCTRL_SAIF0_CLKGATE                   (1 << 31)
+#define        CLKCTRL_SAIF0_BUSY                      (1 << 29)
+#define        CLKCTRL_SAIF0_DIV_FRAC_EN               (1 << 16)
+#define        CLKCTRL_SAIF0_DIV_MASK                  0xffff
+#define        CLKCTRL_SAIF0_DIV_OFFSET                0
+
+#define        CLKCTRL_TV_CLK_TV108M_GATE              (1 << 31)
+#define        CLKCTRL_TV_CLK_TV_GATE                  (1 << 30)
 
 #define        CLKCTRL_ETM_CLKGATE                     (1 << 31)
 #define        CLKCTRL_ETM_BUSY                        (1 << 29)
@@ -169,13 +192,14 @@
 #define        CLKCTRL_FRAC_FRAC_OFFSET                0
 #define        CLKCTRL_FRAC0_CPU                       0
 #define        CLKCTRL_FRAC0_EMI                       1
-#define        CLKCTRL_FRAC0_IO1                       2
+#define        CLKCTRL_FRAC0_PIX                       2
 #define        CLKCTRL_FRAC0_IO0                       3
+#define        CLKCTRL_FRAC1_VID                       3
 
 #define        CLKCTRL_CLKSEQ_BYPASS_ETM               (1 << 8)
 #define        CLKCTRL_CLKSEQ_BYPASS_CPU               (1 << 7)
 #define        CLKCTRL_CLKSEQ_BYPASS_EMI               (1 << 6)
-#define        CLKCTRL_CLKSEQ_BYPASS_SSP               (1 << 5) /* FIXME: 
bypass SSP0 and SSP1? */
+#define        CLKCTRL_CLKSEQ_BYPASS_SSP               (1 << 5)
 #define        CLKCTRL_CLKSEQ_BYPASS_GPMI              (1 << 4)
 #define        CLKCTRL_CLKSEQ_BYPASS_IR                (1 << 3)
 #define        CLKCTRL_CLKSEQ_BYPASS_PIX               (1 << 1)
@@ -194,7 +218,4 @@
 #define        CLKCTRL_VERSION_STEP_MASK               0xffff
 #define        CLKCTRL_VERSION_STEP_OFFSET             0
 
-/* Compatibility */
-#define CLKCTRL_CLKSEQ_BYPASS_SSP0 CLKCTRL_CLKSEQ_BYPASS_SSP
-
 #endif /* __MX23_REGS_CLKCTRL_H__ */

Best regards,
Marek Vasut
Otavio Salvador - Nov. 25, 2012, 2:57 a.m.
On Sun, Nov 25, 2012 at 12:54 AM, Marek Vasut <marex@denx.de> wrote:
> Dear Otavio Salvador,
>
>> On Sat, Nov 24, 2012 at 10:21 PM, Marek Vasut <marex@denx.de> wrote:
>> > Add register definitions for the i.MX23 power control block and
>> > clock control block. These are essential for the basic bootstrap
>> > of the i.MX23. Also, properly include them in imx-regs.h .
>> >
>> > Signed-off-by: Marek Vasut <marex@denx.de>
>> > Cc: Stefano Babic <sbabic@denx.de>
>>
>> Please don't merge it now as this has been already done in my branch with
>> mx23.
>
> I'm attaching a proper diff against your branch. There are multiple wrong and
> missing bits in your branch. This patch is done by processing the FSL-provided
> header file and cross-checking with the datasheet.
>
> So, this patch is right, yours is wrong. Sorry.

I am not saying mine is perfect, far from it. And we can fix it in the
branch but please don't push it until we finish mx23 bootstrap.

Let's work in same code, not duplicate work...
Marek Vasut - Nov. 25, 2012, 3:06 a.m.
Dear Otavio Salvador,

> On Sun, Nov 25, 2012 at 12:54 AM, Marek Vasut <marex@denx.de> wrote:
> > Dear Otavio Salvador,
> > 
> >> On Sat, Nov 24, 2012 at 10:21 PM, Marek Vasut <marex@denx.de> wrote:
> >> > Add register definitions for the i.MX23 power control block and
> >> > clock control block. These are essential for the basic bootstrap
> >> > of the i.MX23. Also, properly include them in imx-regs.h .
> >> > 
> >> > Signed-off-by: Marek Vasut <marex@denx.de>
> >> > Cc: Stefano Babic <sbabic@denx.de>
> >> 
> >> Please don't merge it now as this has been already done in my branch
> >> with mx23.
> > 
> > I'm attaching a proper diff against your branch. There are multiple wrong
> > and missing bits in your branch. This patch is done by processing the
> > FSL-provided header file and cross-checking with the datasheet.
> > 
> > So, this patch is right, yours is wrong. Sorry.
> 
> I am not saying mine is perfect, far from it. And we can fix it in the
> branch but please don't push it until we finish mx23 bootstrap.
> 
> Let's work in same code, not duplicate work...

I still don't see any argument against applying this patch -- other than the 
fact it will break some out-of-tree port.

Best regards,
Marek Vasut
Otavio Salvador - Nov. 25, 2012, 6:10 p.m.
On Sun, Nov 25, 2012 at 1:06 AM, Marek Vasut <marex@denx.de> wrote:
> I still don't see any argument against applying this patch -- other than the
> fact it will break some out-of-tree port.

Isn't it good enough?

You know about my port; you know where it is and in fact you've been
helping guiding me about the technical issues I have no knowledge
about. So what is the point in merge something which is know to break
other tree?

I hope you and Stefano hold it. I would love if you could send it for
merging in my tree and when it is done we merge it.
Marek Vasut - Nov. 25, 2012, 6:17 p.m.
Dear Otavio Salvador,

> On Sun, Nov 25, 2012 at 1:06 AM, Marek Vasut <marex@denx.de> wrote:
> > I still don't see any argument against applying this patch -- other than
> > the fact it will break some out-of-tree port.
> 
> Isn't it good enough?

It is not good enough, we can not care about out-of-tree ports. If we had to 
consider every single out-of-tree patchset for U-Boot, we'd be stuck in one 
place.

> You know about my port; you know where it is and in fact you've been
> helping guiding me about the technical issues I have no knowledge
> about.

Yes, I did know about it. But there was no activity recently, so I started 
pushing it.

> So what is the point in merge something which is know to break
> other tree?

See above for the explanation.

> I hope you and Stefano hold it. I would love if you could send it for
> merging in my tree and when it is done we merge it.

You can rebase your tree on top of mainline, no problem with that.

Best regards,
Marek Vasut
Stefano Babic - Dec. 4, 2012, 7:59 a.m.
On 25/11/2012 01:21, Marek Vasut wrote:
> Add register definitions for the i.MX23 power control block and
> clock control block. These are essential for the basic bootstrap
> of the i.MX23. Also, properly include them in imx-regs.h .
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Hi Marek, Hi Otavio,

>  arch/arm/include/asm/arch-mxs/imx-regs.h          |    5 +
>  arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h |  221 +++++++++++++
>  arch/arm/include/asm/arch-mxs/regs-power-mx23.h   |  357 +++++++++++++++++++++
>  3 files changed, 583 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
>  create mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
> 

The main (and only issue) here is that there is not yet a board with
MX23 in u-boot to use this code. Then this is dead code, and I cannot
merge it now - I will postpone this patch.

The best way to add support for this SOC is, as usually, to get a bunch
of patches with the last ones for a board using the SOC. Else we are
unsure that the code we introduce can be really used later.

Best regards,
Stefano Babic
Otavio Salvador - Dec. 4, 2012, 11:09 a.m.
On Tue, Dec 4, 2012 at 5:59 AM, Stefano Babic <sbabic@denx.de> wrote:

> On 25/11/2012 01:21, Marek Vasut wrote:
> > Add register definitions for the i.MX23 power control block and
> > clock control block. These are essential for the basic bootstrap
> > of the i.MX23. Also, properly include them in imx-regs.h .
> >
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
>
> Hi Marek, Hi Otavio,
>
> >  arch/arm/include/asm/arch-mxs/imx-regs.h          |    5 +
> >  arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h |  221 +++++++++++++
> >  arch/arm/include/asm/arch-mxs/regs-power-mx23.h   |  357
> +++++++++++++++++++++
> >  3 files changed, 583 insertions(+)
> >  create mode 100644 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
> >  create mode 100644 arch/arm/include/asm/arch-mxs/regs-power-mx23.h
> >
>
> The main (and only issue) here is that there is not yet a board with
> MX23 in u-boot to use this code. Then this is dead code, and I cannot
> merge it now - I will postpone this patch.
>
> The best way to add support for this SOC is, as usually, to get a bunch
> of patches with the last ones for a board using the SOC. Else we are
> unsure that the code we introduce can be really used later.
>

I agree; I have applied it in my tree and will send it together with other
patches when I have something useful.

Patch

diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 9764041..563e4a3 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -37,6 +37,11 @@ 
 #include <asm/arch/regs-ssp.h>
 #include <asm/arch/regs-timrot.h>
 
+#ifdef CONFIG_MX23
+#include <asm/arch/regs-clkctrl-mx23.h>
+#include <asm/arch/regs-power-mx23.h>
+#endif
+
 #ifdef CONFIG_MX28
 #include <asm/arch/regs-clkctrl-mx28.h>
 #include <asm/arch/regs-power-mx28.h>
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 0000000..ba2dae2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,221 @@ 
+/*
+ * Freescale i.MX23 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX23_REGS_CLKCTRL_H__
+#define __MX23_REGS_CLKCTRL_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_BUSY			(1 << 29)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
+#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
+#define	CLKCTRL_PIX_BUSY			(1 << 29)
+#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
+#define	CLKCTRL_PIX_DIV_MASK			0xfff
+#define	CLKCTRL_PIX_DIV_OFFSET			0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_IR_CLKGATE			(1 << 31)
+#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
+#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
+#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
+#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
+#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
+#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
+#define	CLKCTRL_IR_IR_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
+#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
+#define	CLKCTRL_ETM_DIV_MASK			0x3f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_PIX			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_VID			3
+
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
+
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX23_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
new file mode 100644
index 0000000..9166b97
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -0,0 +1,357 @@ 
+/*
+ * Freescale i.MX23 Power Controller Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX23_REGS_POWER_H__
+#define __MX23_REGS_POWER_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_power_reset)
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+};
+#endif
+
+#define	POWER_CTRL_CLKGATE				(1 << 30)
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 28)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2			(1 << 20)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_VDAC_DUMP_CTRL			(1 << 13)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_CHARGER_RESISTORS		(1 << 21)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_USE_EXTERN_R			(1 << 17)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xff << 16)
+#define	POWER_SPEED_STATUS_OFFSET			16
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX23_REGS_POWER_H__ */