Patchwork [U-Boot] mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registers

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Submitter Marek Vasut
Date Nov. 25, 2012, 12:03 a.m.
Message ID <1353801801-13118-1-git-send-email-marex@denx.de>
Download mbox | patch
Permalink /patch/201492/
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Comments

Marek Vasut - Nov. 25, 2012, 12:03 a.m.
These registers don't have _SET, _CLR and _TOG at the respective offsets
available, these registers has to be toggled via R-M-W if needed. Thus do
not export these offsets anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
Otavio Salvador - Nov. 26, 2012, 4:26 p.m.
On Sat, Nov 24, 2012 at 10:03 PM, Marek Vasut <marex@denx.de> wrote:
> These registers don't have _SET, _CLR and _TOG at the respective offsets
> available, these registers has to be toggled via R-M-W if needed. Thus do
> not export these offsets anymore.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>

Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Stefano Babic - Dec. 4, 2012, 7:52 a.m.
On 25/11/2012 01:03, Marek Vasut wrote:
> These registers don't have _SET, _CLR and _TOG at the respective offsets
> available, these registers has to be toggled via R-M-W if needed. Thus do
> not export these offsets anymore.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Patch

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index b662fbe..23e9adc 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -31,9 +31,11 @@ 
 #ifndef	__ASSEMBLY__
 struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
-	mxs_reg_32(hw_clkctrl_pll0ctrl1)	/* 0x10 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
 	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
-	mxs_reg_32(hw_clkctrl_pll1ctrl1)	/* 0x30 */
+	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
+	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
 	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
 	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */