From patchwork Sat Nov 24 14:07:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 201470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BAC4C2C008C for ; Sun, 25 Nov 2012 01:07:27 +1100 (EST) Received: from localhost ([::1]:43972 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcGOC-0002ta-F4 for incoming@patchwork.ozlabs.org; Sat, 24 Nov 2012 09:07:24 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcGO4-0002tU-Pd for qemu-devel@nongnu.org; Sat, 24 Nov 2012 09:07:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TcGO3-0004m5-Lx for qemu-devel@nongnu.org; Sat, 24 Nov 2012 09:07:16 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:48856) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TcGO3-0004lx-Fm for qemu-devel@nongnu.org; Sat, 24 Nov 2012 09:07:15 -0500 Received: from 37-8-177-151.coucou-networks.fr ([37.8.177.151] helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TcGO1-000547-In; Sat, 24 Nov 2012 15:07:14 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TcGNr-0002SP-8E; Sat, 24 Nov 2012 15:07:03 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 24 Nov 2012 15:07:01 +0100 Message-Id: <1353766021-7843-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH for 1.3] target-i386: enable SSSE3 TCG support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org SSSE3 support has been added to TCG more than 4 years ago in commit 4242b1bd8acc19aaaacffdaad4ac23213d72a72b. It has been disabled by mistake in commit 551a2dec8fa55006a68393b9d6fb63577d2b3f1c. Signed-off-by: Aurelien Jarno Reviewed-by: Andreas Färber --- target-i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) SSE4.1 and SSE4.2 are wrongly disabled too, but some instructions from SSE4.2 (I haven't investigated more yet) are wrongly emulated, which causes some crashes now that GLIBC is using them through gnu indirect functions. diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 64c3491..68f6f5d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -315,7 +315,7 @@ typedef struct x86_def_t { /* missing: CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ - CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ + CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ CPUID_EXT_HYPERVISOR) /* missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,