From patchwork Fri Nov 23 15:48:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 201386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 499BD2C008A for ; Sat, 24 Nov 2012 04:35:06 +1100 (EST) Received: from localhost ([::1]:50055 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbvVk-0008OK-35 for incoming@patchwork.ozlabs.org; Fri, 23 Nov 2012 10:49:48 -0500 Received: from eggs.gnu.org ([208.118.235.92]:35062) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbvUk-0006CN-Ho for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TbvUa-0006jT-7n for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:46 -0500 Received: from mx1.redhat.com ([209.132.183.28]:8680) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TbvUZ-0006j3-WC for qemu-devel@nongnu.org; Fri, 23 Nov 2012 10:48:36 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id qANFmZi7005134 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 23 Nov 2012 10:48:35 -0500 Received: from rincewind.home.kraxel.org (ovpn-116-26.ams2.redhat.com [10.36.116.26]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id qANFmXVB000647; Fri, 23 Nov 2012 10:48:34 -0500 Received: by rincewind.home.kraxel.org (Postfix, from userid 500) id 71906408C4; Fri, 23 Nov 2012 16:48:32 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Fri, 23 Nov 2012 16:48:25 +0100 Message-Id: <1353685711-24573-15-git-send-email-kraxel@redhat.com> In-Reply-To: <1353685711-24573-1-git-send-email-kraxel@redhat.com> References: <1353685711-24573-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Gerd Hoffmann Subject: [Qemu-devel] [PATCH 14/20] acpi: cleanup ich9 memory region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Nothing left to do, everything handled by subregions, we can zap the reaw/write handlers now. Signed-off-by: Gerd Hoffmann --- hw/acpi_ich9.c | 125 +------------------------------------------------------- 1 files changed, 1 insertions(+), 124 deletions(-) diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c index cdfa266..4faa18d 100644 --- a/hw/acpi_ich9.c +++ b/hw/acpi_ich9.c @@ -42,10 +42,6 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) #define ICH9_DEBUG(fmt, ...) do { } while (0) #endif -static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len, - uint32_t val); -static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len); - static void pm_update_sci(ICH9LPCPMRegs *pm) { int sci_level, pm1a_sts; @@ -71,125 +67,6 @@ static void ich9_pm_update_sci_fn(ACPIREGS *regs) pm_update_sci(pm); } -static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) -{ - switch (addr & ICH9_PMIO_MASK) { - default: - break; - } - - ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val); -} - -static uint32_t pm_ioport_readb(void *opaque, uint32_t addr) -{ - uint32_t val = 0; - - switch (addr & ICH9_PMIO_MASK) { - default: - val = 0; - break; - } - ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val); - return val; -} - -static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) -{ - switch (addr & ICH9_PMIO_MASK) { - default: - pm_ioport_write_fallback(opaque, addr, 2, val); - break; - } - ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val); -} - -static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) -{ - uint32_t val; - - switch (addr & ICH9_PMIO_MASK) { - default: - val = pm_ioport_read_fallback(opaque, addr, 2); - break; - } - ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val); - return val; -} - -static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) -{ - switch (addr & ICH9_PMIO_MASK) { - default: - pm_ioport_write_fallback(opaque, addr, 4, val); - break; - } - ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val); -} - -static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) -{ - uint32_t val; - - switch (addr & ICH9_PMIO_MASK) { - default: - val = pm_ioport_read_fallback(opaque, addr, 4); - break; - } - ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val); - return val; -} - -static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len, - uint32_t val) - { - int subsize = (len == 4) ? 2 : 1; - IOPortWriteFunc *ioport_write = - (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb; - - int i; - - for (i = 0; i < len; i += subsize) { - ioport_write(opaque, addr, val); - val >>= 8 * subsize; - } -} - -static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len) -{ - int subsize = (len == 4) ? 2 : 1; - IOPortReadFunc *ioport_read = - (subsize == 2) ? pm_ioport_readw : pm_ioport_readb; - - uint32_t val; - int i; - - val = 0; - for (i = 0; i < len; i += subsize) { - val <<= 8 * subsize; - val |= ioport_read(opaque, addr); - } - - return val; -} - -static const MemoryRegionOps pm_io_ops = { - .old_portio = (MemoryRegionPortio[]) { - { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 1, - .read = pm_ioport_readb, .write = pm_ioport_writeb }, - { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 2, - .read = pm_ioport_readw, .write = pm_ioport_writew }, - { .offset = 0, .len = ICH9_PMIO_SIZE, .size = 4, - .read = pm_ioport_readl, .write = pm_ioport_writel }, - PORTIO_END_OF_LIST(), - }, - .valid.min_access_size = 1, - .valid.max_access_size = 4, - .impl.min_access_size = 1, - .impl.max_access_size = 4, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) { ICH9LPCPMRegs *pm = opaque; @@ -332,7 +209,7 @@ static void pm_powerdown_req(Notifier *n, void *opaque) void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3) { - memory_region_init_io(&pm->io, &pm_io_ops, pm, "ich9-pm", ICH9_PMIO_SIZE); + memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE); acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);