Patchwork RFA: contribute Synopsis DesignWare ARC port

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Submitter Joern Rennecke
Date Nov. 22, 2012, 8:22 p.m.
Message ID <20121122152226.tt1mhpsveogwwkww-nzlynne@webmail.spamcop.net>
Download mbox | patch
Permalink /patch/201186/
State New
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Comments

Joern Rennecke - Nov. 22, 2012, 8:22 p.m.
libgcc:

2012-10-09  Joern Rennecke  <joern.rennecke@embecosm.com>

        * config.host (arc-*-elf*, arc*-*-linux-uclibc*): New configurations.
gcc:

2012-11-22  Joern Rennecke  <joern.rennecke@embecosm.com>
            Brendan Kehoe  <brendan@zen.org>

        * config.gcc (arc-*-elf*, arc*-*-linux-uclibc*): New configurations.
        * doc/install.texi (--with-cpu): Mention ARC.
        (arc-*-elf32): New paragraph.
        (arc-linux-uclibc): Likewise.
        * doc/md.texi (Machine Constraints): Add ARC part.
        * doc/invoke.texi: (menu): Add ARC Options.
        (Machine Dependent Options) <ARC Options>: Add synopsis.
        (node ARC Options): Add.
        * doc/extend.texi (long_call / short_call attribute): Add ARC.

gcc/testsuite:

2012-11-22  Joern Rennecke  <joern.rennecke@embecosm.com>

        * gcc.c-torture/execute/20101011-1.c [__arc__] (DO_TEST): Define as 0.
        * gcc.dg/torture/pr37868.c: Also skip for arc*-*-*.
        * gcc.dg/stack-usage-1.c [__arc__] (SIZE): Define.

libstdc++-v3:

2012-08-16  Joern Rennecke  <joern.rennecke@embecosm.com>

        * acinclude.m4 (GLIBCXX_ENABLE_SJLJ_EXCEPTIONS): Also check for
        _Unwind_SjLj_Register when deciding if to set enable_sjlj_exceptions.
        * configure: Regenerate.

gcc:

2012-11-22  Saurabh Verma  <saurabh.verma@codito.com>
            Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
            Joern Rennecke  <joern.rennecke@embecosm.com>
            Muhammad Khurram Riaz <khurram.riaz@arc.com>
            Brendan Kehoe  <brendan@zen.org>
            Michael Eager  <eager@eagercon.com>

        * config/arc, common/config/arc: New directories.

gcc/testsuite:

2012-08-28  Joern Rennecke  <joern.rennecke@embecosm.com>

        * gcc.target/arc: New directory.

libgcc:

2012-10-18  Joern Rennecke  <joern.rennecke@embecosm.com>
            Brendan Kehoe  <brendan@zen.org>

        * libgcc/config/arc: New directory.
2012-10-31  Joern Rennecke  <joern.rennecke@embecosm.com>

contrib:
	* config-list.mk (LIST): Add arc-elf32OPT-with-cpu=arc600,
	arc-elf32OPT-with-cpu=arc700 and
	arc-linux-uclibcOPT-with-cpu=arc700 .

Index: config-list.mk
===================================================================
--- config-list.mk	(revision 193034)
+++ config-list.mk	(working copy)
@@ -1,5 +1,5 @@
 # Run tests covering all config.gcc cases.
-host_options='--with-mpc=/opt/cfarm/mpc' # gcc10
+#host_options='--with-mpc=/opt/cfarm/mpc' # gcc10
 TEST=all-gcc
 # Make sure you have a recent enough gcc (with ada support) in your path so
 # that --enable-werror-always will work.
@@ -13,6 +13,8 @@
 # v850e1-elf is rejected by config.sub
 LIST = alpha-linux-gnu alpha-freebsd6 alpha-netbsd alpha-openbsd \
   alpha64-dec-vms alpha-dec-vms am33_2.0-linux \
+  arc-elf32OPT-with-cpu=arc600 arc-elf32OPT-with-cpu=arc700 \
+  arc-linux-uclibcOPT-with-cpu=arc700 \
   arm-wrs-vxworks arm-netbsdelf \
   arm-linux-androideabi arm-uclinux_eabi arm-eabi \
   arm-symbianelf avr-rtems avr-elf \
Steven Bosscher - Nov. 24, 2012, 11:17 p.m.
On Thu, Nov 22, 2012 at 9:22 PM, Joern Rennecke wrote:
(nothing but a ChangeLog :-)

Looking at the ARC port a bit, and IMHO it doesn't look very messy...

First some general comments:

This target apparently wants to play tricks with reload (e.g.
arc_preserve_reload_p). IMHO at this point ports that don't work with
LRA should not be accepted.

TARGET_EXPAND_ADDDI is not covered in any test. Actually most target
options are not covered.

Can't the following option be just removed:
mold-di-patterns
Target Var(TARGET_OLD_DI_PATTERNS)
enable use of old DI patterns that have presumably been obsoleted by
subreg lowering.

There quite some old cruft that should be cleaned up. A few examples:

1. Things that probably worked before GCC3 but shouldn't be in a new port:
/*    /\* Compute LOG_LINKS.  *\/ */
/*    for (bb = 0; bb < current_nr_blocks; bb++) */
/*      compute_block_backward_dependences (bb); */

2. Old scheduler description:
;; Function units of the ARC

;; (define_function_unit {name} {num-units} {n-users} {test}
;;                       {ready-delay} {issue-delay} [{conflict-list}])
(etc...)

3. Presumably no longer applicable comments if this port is supposed
to be part of the FSF repo:
;; *** N.B.: the use of '* return...' in "*movsi_insn", et al, rely
;; on ARC-local changes to genoutput.c's process_template() function



Some random observations in config/arc/arc.c:
arc_dead_or_set_postreload_p() and the related functions is not used AFAICT.
Many functions (most?) have no leading comments.



About config/arc/arc.md:

What's this comment about?
;;  ashwin : include options.h from build dir
;; (include "arc.c")

The is_NON_SIBCALL attribute appears to be unused. If it can be
removed, then so can the is_SIBCALL attribute.
How is the "*millicode_sibthunk_ld" pattern used?

What are the commented-out patterns (e.g. "*adc_0") for?

Before the sibcall and return_i patterns:
; Since the demise of REG_N_SETS, it is no longer possible to find out
; in the prologue / epilogue expanders how many times blink is set.
I don't understand this, REG_N_SETS still exists.

C-style comment in a .md file (does that even work??):
/* Store a value to directly to memory.  The location might also be cached.
   Since the cached copy can cause a write-back at unpredictable times,
   we first write cached, then we write uncached.  */

Why are there patterns that have a "switch (which_alternative)" to
emit the insn template, instead of an "@..." string? See e.g.
(define_insn "*zero_extendhisi2_i" and "*zero_extendqisi2_ac".


It seems to me that a bit of cleaning up is in order before this port
is accepted.

Ciao!
Steven
Joern Rennecke - Nov. 25, 2012, 5:47 p.m.
Quoting Steven Bosscher <stevenb.gcc@gmail.com>:

> On Thu, Nov 22, 2012 at 9:22 PM, Joern Rennecke wrote:
> (nothing but a ChangeLog :-)

There was also some code.  Did you want a press release?  I'm afraid I'm
not good at these.
FWIW, Synopsys has the FSF paperwork in place, and Embecosm does ongoing
GCC work for them, so that should also cover the maintenance issue.
The port as posted here works without the final.c patches, albeit
the resulting compiler it is inferior in performance of the generated
code compared to one with scheduling/alignment aware instruction sizing.

> Looking at the ARC port a bit, and IMHO it doesn't look very messy...
>
> First some general comments:
>
> This target apparently wants to play tricks with reload (e.g.
> arc_preserve_reload_p).

That's just a performance optimization; it requires an entry in target.def
(plus documentation) and a simple two-liner in reload.c to actually be
enabled, but I thought this is better left to when we have better visibility
of how well LRA plays out, and besides, getting branch shortening sorted
out was - and still is - a much more pressing issue.

> IMHO at this point ports that don't work with
> LRA should not be accepted.

That's is quite an imposition, considering LRA is only a few days in mainline,
supports only x86 so far, and is still settling in.
I tried enabling LRA for ARC, but quickly found that it won't allow libgcc to
configure.  See PR rtl-optimization/55464.
I' sure these kinks can be worked out, but can the required patches to lra
still go in in phase 3?

> TARGET_EXPAND_ADDDI is not covered in any test. Actually most target
> options are not covered.

We'll look into adding more tests.

> Can't the following option be just removed:
> mold-di-patterns
> Target Var(TARGET_OLD_DI_PATTERNS)
> enable use of old DI patterns that have presumably been obsoleted by
> subreg lowering.

I've been waiting for feedback on this.  Well, on and off - I have changed
employers in the meantime a few times, since I conditionalized these patterns
in 2008.  I suppose it's safe to remove this code now, and on the off chance
that someone misses it, I can investigate why and add back/replace whatever
was useful.

> There quite some old cruft that should be cleaned up. A few examples:
..
> /*    /\* Compute LOG_LINKS.  *\/ */
..
> 2. Old scheduler description:

deleted.

> 3. Presumably no longer applicable comments if this port is supposed
> to be part of the FSF repo:
> ;; *** N.B.: the use of '* return...' in "*movsi_insn", et al, rely
> ;; on ARC-local changes to genoutput.c's process_template() function

That comment indeed became obsolete with r192457, this bit of infrastructure
has been in mainline since mid-October.

> Some random observations in config/arc/arc.c:
> arc_dead_or_set_postreload_p() and the related functions is not used AFAICT.
related functions?  I count one.  But you are right, this stuff became
orphaned when I removed the old-style peepholes.

> Many functions (most?) have no leading comments.

Most do have leading comments.  Some functions are just vanilla target
macro / hook implementations, and I remember we said that in this case,
it's better not to copy the description from tm.texi - it's just creates
unnecessary attack surface for code rot (comment rot?).

> About config/arc/arc.md:
>
> What's this comment about?
> ;;  ashwin : include options.h from build dir
> ;; (include "arc.c")

I haven't the foggiest.  It's part of the Codito 'heritage'.  Deleted.

> The is_NON_SIBCALL attribute appears to be unused. If it can be
> removed, then so can the is_SIBCALL attribute.

It is used, via the CALL_ATTR macro.

> How is the "*millicode_sibthunk_ld" pattern used?

It is generated by the epilogue expander when optimizing for space and a
lot of registers need to be restored.

> What are the commented-out patterns (e.g. "*adc_0") for?

Stuff that combine doesn't do right.  Can't really hop to fix this in 4.8 .
adc_0 is using add with carry of 0, which is interesting for some flag
arithmetic.

> Before the sibcall and return_i patterns:
> ; Since the demise of REG_N_SETS, it is no longer possible to find out
> ; in the prologue / epilogue expanders how many times blink is set.
> I don't understand this, REG_N_SETS still exists.

True, there's still a REG_N_SETS here, even if it cannot be used in a port
the way it used to.  I have clarified the comment.

> C-style comment in a .md file (does that even work??):
> /* Store a value to directly to memory.  The location might also be cached.
>    Since the cached copy can cause a write-back at unpredictable times,
>    we first write cached, then we write uncached.  */

Well, it's been working for years, else I'd have been alerted to this
typo rather quickly.

> Why are there patterns that have a "switch (which_alternative)" to
> emit the insn template, instead of an "@..." string? See e.g.
> (define_insn "*zero_extendhisi2_i" and "*zero_extendqisi2_ac".

These two patterns are indeed simpler with "@" syntax.
The rest are not - they either have non-trivial code in the switch,
or have a lot of alternatives with identical output patterns.

> It seems to me that a bit of cleaning up is in order before this port
> is accepted.

I have attached a new arc.c .
Joern Rennecke - Nov. 25, 2012, 5:49 p.m.

Patch

Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	(revision 2691)
+++ gcc/config.gcc	(working copy)
@@ -800,7 +800,7 @@ 
     *) echo 'Unknown thread configuration for VxWorks'; exit 1 ;;
   esac
   ;;
-*-*-elf)
+*-*-elf|arc-*-elf*)
   # Assume that newlib is being used and so __cxa_atexit is provided.
   default_use_cxa_atexit=yes
   use_gcc_stdint=wrap
@@ -852,6 +852,39 @@ 
 	tm_file="${tm_file} vms/vms.h alpha/vms.h"
 	tmake_file="${tmake_file} alpha/t-vms"
 	;;
+arc-*-elf*)
+	extra_headers="arc-simd.h"
+	tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
+	tmake_file="arc/t-arc-newlib arc/t-arc"
+	case x"${with_cpu}" in
+	  xarc600|xarc601|xarc700)
+		target_cpu_default="TARGET_CPU_$with_cpu"
+		;;
+	esac
+	;;
+arc*-*-linux-uclibc*)
+	extra_headers="arc-simd.h"
+	tm_file="dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h ${tm_file}"
+	tmake_file="${tmake_file} arc/t-arc-uClibc arc/t-arc"
+	case x"${with_cpu}" in
+	  xarc600|xarc601|xarc700)
+		target_cpu_default="TARGET_CPU_$with_cpu"
+		;;
+	esac
+	if test x${with_endian} = x; then
+		case ${target} in
+		arc*be-*-* | arc*eb-*-*)	with_endian=big ;;
+		*)				with_endian=little ;;
+		esac
+	fi
+	case ${with_endian} in
+	big|little)		;;
+	*)	echo "with_endian=${with_endian} not supported."; exit 1 ;;
+	esac
+	case ${with_endian} in
+	big*)	tm_defines="DRIVER_ENDIAN_SELF_SPECS=\\\"%{!EL:%{!mlittle-endian:-mbig-endian}}\\\" ${tm_defines}"
+	esac
+        ;;
 arm-wrs-vxworks)
 	tm_file="elfos.h arm/elf.h arm/aout.h ${tm_file} vx-common.h vxworks.h arm/vxworks.h"
 	extra_options="${extra_options} arm/vxworks.opt"
@@ -3140,6 +3173,17 @@ 
 		done
 		;;
 
+	arc*-*-*) # was:	arc*-*-linux-uclibc)
+		supported_defaults="cpu"
+		case $with_cpu in
+		  arc600|arc601|arc700)
+			;;
+		  *) echo "Unknown cpu type"
+			exit 1
+			;;
+		esac
+		;;
+
 	arm*-*-*)
 		supported_defaults="arch cpu float tune fpu abi mode tls"
 		for which in cpu tune; do
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 2691)
+++ gcc/doc/md.texi	(working copy)
@@ -1731,6 +1731,54 @@  The high part (bits 12 and upwards) of t
 @end table
 
 
+@item ARC ---@file{config/arc/constraints.md}
+@table @code
+@item q
+Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
+@code{r12}-@code{r15}.  This constraint can only match when the @option{-mq}
+option is in effect.
+
+@item e
+Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
+instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
+This constraint can only match when the @option{-mq}
+option is in effect.
+@item D
+ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
+
+@item I
+A signed 12-bit integer constant.
+
+@item Cal
+constant for arithmetic/logical operations.  This might be any constant
+that can be put into a long immediate by the assmbler or linker without
+involving a PIC relocation.
+
+@item K
+A 3-bit unsigned integer constant.
+
+@item L
+A 6-bit unsigned integer constant.
+
+@item CnL
+One's complement of a 6-bit unsigned integer constant.
+
+@item CmL
+Two's complement of a 6-bit unsigned integer constant.
+
+@item M
+A 5-bit unsigned integer constant.
+
+@item O
+A 7-bit unsigned integer constant.
+
+@item P
+A 8-bit unsigned integer constant.
+
+@item H
+Any const_double value.
+@end table
+
 @item ARM family---@file{config/arm/constraints.md}
 @table @code
 @item w
Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 2691)
+++ gcc/doc/extend.texi	(working copy)
@@ -2783,7 +2783,7 @@  least version 2.20.1), and GNU C library
 
 @item interrupt
 @cindex interrupt handler functions
-Use this attribute on the ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
+Use this attribute on the ARC, ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
 RL78, RX and Xstormy16 ports to indicate that the specified function is an
 interrupt handler.  The compiler generates function entry and exit
 sequences suitable for use in an interrupt handler when this attribute
@@ -2793,6 +2793,16 @@  least version 2.20.1), and GNU C library
 Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
 and SH processors can be specified via the @code{interrupt_handler} attribute.
 
+Note, on the ARC, you must specify the kind of interrupt to by handled
+in a parameter to the interrupt attribute like this:
+
+@smallexample
+void f () __attribute__ ((interrupt ("ilink1")));
+@end smallexample
+
+Permissible values for this parameter are: @w{@code{ilink1}} and
+@w{@code{ilink2}}.
+
 Note, on the AVR, the hardware globally disables interrupts when an
 interrupt is executed.  The first instruction of an interrupt handler
 declared with this attribute is a @code{SEI} instruction to
@@ -2963,7 +2973,7 @@  handlers intended to be used with the @c
 @item long_call/short_call
 @cindex indirect calls on ARM
 This attribute specifies how a particular function is called on
-ARM and Epiphany.  Both attributes override the
+ARC, ARM and Epiphany.  Both attributes override the
 @option{-mlong-calls} (@pxref{ARM Options})
 command-line switch and @code{#pragma long_calls} settings.  The
 @code{long_call} attribute indicates that the function might be far
Index: gcc/doc/install.texi
===================================================================
--- gcc/doc/install.texi	(revision 2691)
+++ gcc/doc/install.texi	(working copy)
@@ -1179,8 +1179,8 @@  Specify that the target supports TLS (Th
 @itemx --with-cpu-64=@var{cpu}
 Specify which cpu variant the compiler should generate code for by default.
 @var{cpu} will be used as the default value of the @option{-mcpu=} switch.
-This option is only supported on some targets, including ARM, i386, M68k,
-PowerPC, and SPARC@.  The @option{--with-cpu-32} and
+This option is only supported on some targets, including ARC, ARM, i386, M68k,
+PowerPC, and SPARC@.  It is mandatory for ARC@.  The @option{--with-cpu-32} and
 @option{--with-cpu-64} options specify separate default CPUs for
 32-bit and 64-bit modes; these options are only supported for i386,
 x86-64 and PowerPC.
@@ -3147,6 +3147,22 @@  versions before @code{alpha*-dec-osf4} a
 
 @html
 <hr />
+@end html
+@heading @anchor{arc-x-elf32}arc-*-elf32
+
+Use @samp{configure --target=arc-elf32 --with-cpu=@var{cpu} --enable-languages="c,c++"}
+to configure GCC, with @var{cpu} being one of @samp{arc600}, @samp{arc601},
+or @samp{arc700}@.
+
+@html
+<hr />
+@end html
+@heading @anchor{arc-linux-uclibc}arc-linux-uclibc
+
+Use @samp{configure --target=arc-linux-uclibc --with-cpu=arc700 --enable-languages="c,c++"} to configure GCC@.
+
+@html
+<hr />
 @end html
 @heading @anchor{arm-x-eabi}arm-*-eabi
 ARM-family processors.  Subtargets that use the ELF object format
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 2691)
+++ gcc/doc/invoke.texi	(working copy)
@@ -484,6 +484,24 @@  cpp(1), gcov(1), as(1), ld(1), gdb(1), a
 -mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol
 -msplit-vecmove-early -m1reg-@var{reg}}
 
+@emph{ARC Options}
+@gccoptlist{-mbig-endian -mlittle-endian -mno-cond-exec -mA5 -mA6 -mARC600 @gol
+-mA7 -mARC700 -mmixed-code -mvolatile-cache -mbarrel-shifter @gol
+-mnorm -mswap -mmul64 -mno-mpy -mEA -msoft-float -mlong-calls @gol
+-mno-brcc -mno-sdata -mno-millicode @gol
+-mspfp -mspfp_compact -mspfp_fast -margonaut @gol
+-mdpfp -mdpfp_compact -mdpfp_fast -mno-dpfp-lrsr @gol
+-msimd -mcpu=@var{cpu} -msize-level=@var{level} -misize @gol
+-multcost=@var{cost} -mtune=@var{cpu} -mindexed-loads @gol
+-mauto-modify-reg -mold-di-patterns -mmul32x16 -m2addr @gol
+-munalign-prob-threshold=@var{probability} -mmedium-calls @gol
+-mannotate-align -malign-call -mRcq -mRcw -mearly-cbranchsi @gol
+-mbbit-peephole @gol
+-mcase-vector-pcrel -mcompact-casesi -mq-class -mexpand-adddi @gol
+-mcrc -mdsp_packa -mdvbf -mmac_d16 -mmac_24 -mtelephony -mxy @gol
+-mlock -mswape -mrtsc @gol
+-mepilogue-cfi -EB -EL -marclinux -marclinux-prof}
+
 @emph{ARM Options}
 @gccoptlist{-mapcs-frame  -mno-apcs-frame @gol
 -mabi=@var{name} @gol
@@ -10715,6 +10733,7 @@  finds any @option{-l} options and any no
 @menu
 * AArch64 Options::
 * Adapteva Epiphany Options::
+* ARC Options::
 * ARM Options::
 * AVR Options::
 * Blackfin Options::
@@ -11042,6 +11061,394 @@  truncating (i.e.@: round towards zero) r
 @option{-march} and @option{-mcpu=}.
 @end table
 
+@node ARC Options
+@subsection ARC Options
+@cindex ARC options
+
+These @samp{-m} options are defined for Synopsys DesignWare ARC:
+
+@c architecture variants
+@table @gcctabopt
+@item -mcpu=@var{cpu}
+@opindex mcpu
+Set architecture type, register usage, and
+instruction scheduling parameters for @var{cpu}.
+There are also shortcut alias options available for backward compatibility and
+convenience.
+Supported values for @var{cpu} are
+
+@table @samp
+@item A5
+@opindex mA5
+Compile for Arctangent-A5.  Alias: @option{-mA5}.
+
+@opindex mA6
+@opindex mARC600
+@item ARC600
+Compile for ARC600.  Aliases: @option{-mA6}, @option{-mARC600}.
+
+@item ARC601
+Compile for ARC601.
+
+@item ARC700
+@opindex mA7
+@opindex mARC700
+Compile for ARC700.  Aliases: @option{-mA7}, @option{-mARC700}.
+This is the default when configured with @samp{--with-cpu=arc700}@.
+@end table
+
+@item -mbig-endian
+@opindex mbig-endian
+@item -EB
+@opindex EB
+Compile code for big endian mode
+
+@item -mlittle-endian
+@opindex mlittle-endian
+@item -EL
+@opindex EL
+Compile code for little endian mode.  This is the default.
+
+@item -mbarrel_shifter
+@opindex mbarrel_shifter
+Generate instructions supported by barrel shifter.  This is the default
+unless @samp{-mcpu=ARC601} is in effect.
+
+@item -mnorm
+@opindex mnorm
+Generate norm instruction.
+This is the default if @samp{-mcpu=ARC700} is in effect.
+
+@item -mswap
+@opindex mswap
+Generate swap instructions.
+
+@item -mmul64
+@opindex mmul64
+Generate mul64 and mulu64 instructions
+This is not valid for @samp{-mcpu=ARC700}.
+
+@item -mno-mpy
+@opindex mno-mpy
+Do not generate mpy instructions for ARC700.
+
+@item -mmul32x16
+@opindex mmul32x16
+Generate 32x16 bit multiply and mac instructions.
+
+@item -mEA
+@opindex mEA
+Generate Extended arithmetic instructions.
+Currently only @code{divaw}, @code{adds}, @code{subs}, and @code{sat16}
+supported.
+This is always enabled for @samp{-mcpu=ARC700}.
+
+@item -mspfp
+@opindex mspfp
+@item -mspfp_compact
+@opindex mspfp_compact
+FPX: Generate Single Precision FPX instructions, tuned for the compact
+implementation.
+
+@item -mspfp_fast
+@opindex mspfp_fast
+FPX: Generate Single Precision FPX instructions, tuned for the fast
+implementation.
+
+@item -margonaut
+@opindex margonaut
+FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions.
+
+@item -mdpfp
+@opindex mdpfp
+@item -mdpfp_compact
+@opindex mdpfp_compact
+FPX: Generate Double Precision FPX instructions, tuned for the compact
+implementation.
+
+@item -mdpfp_fast
+@opindex mdpfp_fast
+FPX: Generate Double Precision FPX instructions, tuned for the fast
+implementation.
+
+@item -mno-dpfp-lrsr
+@opindex mno-dpfp-lrsr
+Disable LR and SR instructions from using FPX extension aux registers.
+
+@item -msimd
+@opindex msimd
+Enable generation of ARC SIMD instructions via target-specific builtins.
+
+@item -msoft-float
+@opindex msoft-float
+This option ignored; it is provided for compatibility purposes only.
+Software floating point code is emitted by default, and this default
+can overridden by FPX options; @samp{mspfp}, @samp{mspfp_compact}, or
+@samp{mspfp_fast} for single precision, and @samp{mdpfp},
+@samp{mdpfp_compact}, or @samp{mdpfp_fast} for double precision.
+
+@c Flags used by the assembler, but for which we define preprocessor
+@c macro symbols as well.
+@item -mcrc
+@opindex mcrc
+Passed down to the assembler to
+enable the variable polynomial CRC extension.
+Also sets the preprocessor symbol @code{__Xcrc}.
+
+@item -mdsp_packa
+@opindex mdsp_packa
+Passed down to the assembler to
+enable the DSP 3.1 Pack A extensions.
+Also sets the preprocessor symbol @code{__Xdsp_packa}.
+
+@item -mdvbf
+@opindex mdvbf
+Passed down to the assembler to
+enable the dual viterbi butterfly extension.
+Also sets the preprocessor symbol @code{__Xdvbf}.
+
+@item -mmac_d16
+@opindex mmac_d16
+Passed down to the assembler.
+Also sets the preprocessor symbol @code{__Xxmac_d16}.
+
+@item -mmac_24
+@opindex mmac_24
+Passed down to the assembler.
+Also sets the preprocessor symbol @code{__Xxmac_24}.
+
+@item -mtelephony
+@opindex mtelephony
+Passed down to the assembler to
+enable dual and single operand instructions for telephony.
+Also sets the preprocessor symbol @code{__Xtelephony}.
+
+@item -mxy
+@opindex mxy
+Passed down to the assembler to
+enable the XY Memory extension (DSP version 3).
+Also sets the preprocessor symbol @code{__Xxy}.
+
+@c ARC700 4.10 extension instructions
+@item -mlock
+@opindex mlock
+Passed down to the assembler to
+enable the Locked Load/Store Conditional extension.
+Also sets the preprocessor symbol @code{__Xlock}.
+
+@item -mswape
+@opindex mswape
+Passed down to the assembler to
+enable the swap byte ordering extension instruction.
+Also sets the preprocessor symbol @code{__Xswape}.
+
+@item -mrtsc
+@opindex mrtsc
+Passed down to the assembler to
+enable the 64-bit Time-Stamp Counter extension instruction
+Also sets the preprocessor symbol @code{__Xrtsc}.
+
+
+
+@item -marclinux
+@opindex marclinux
+Pass -marclinux option through to linker.
+
+@item -marclinux_prof
+@opindex marclinux_prof
+Pass -marclinux_prof option through to linker.
+
+@c semantically relevant code generation options
+@item -mvolatile-cache
+@opindex mvolatile-cache
+Use ordinarily cached memory accesses for volatile references.  This is the
+default.
+
+@item -mno-volatile-cache
+@opindex mno-volatile-cache
+Enable cache bypass for volatile references.
+
+@item -mlong-calls
+@opindex mlong-calls
+Generate call insns as register indirect calls.
+
+@item -mmedium-calls
+@opindex mmedium-calls
+Don't use less than 25 bit addressing range for calls.
+
+@item -mno-sdata
+@opindex mno-sdata
+Do not generate sdata references
+
+@item -mno-epilogue-cfi
+@opindex mno-epilogue-cfi
+Disable generation of call frame information for epilogues.
+
+@item -mepilogue-cfi
+@opindex mepilogue-cfi
+Enable generation of call frame information for epilogues.
+
+@c code generation tuning options
+@item -mtune=@var{cpu}
+@opindex mtune
+Set instruction scheduling parameters for @var{cpu}, overriding any implied
+by @option{-mcpu=}.
+
+Supported values for @var{cpu} are
+
+@table @samp
+@item arc600
+Tune for ARC600 cpu.
+
+@item arc601
+Tune for ARC601 cpu.
+
+@item arc700
+Tune for ARC700 R4.2 Cpu with standard multiplier block.
+
+@item arc700-xmac
+@item ARC725D
+@item ARC750D
+Tune for ARC700 R4.2 Cpu with XMAC block.
+
+@end table
+
+@item -mno-cond-exec
+@opindex mno-cond-exec
+Disable ARCompact specific pass to generate conditional execution instructions.
+Due to delay slot scheduling and interactions between operand numbers,
+literal sizes, instruction lengths, and the support for conditional exection,
+the target-independent pass to generate conditional execution is often lacking,
+so the ARC port has kept a sepcial pass around that tries to find more
+conditional execution generating opportunities after register allocation,
+branch shortening, and delay slot scheduling have been done.  This pass
+generally, but not always, improves performace and code size, at the cost of
+extra compilation time, which is why there is an option to switch it off.
+If you have a problem with call instructions exceeding their allowable
+offset range because they are conditionalized, you should consider using
+@option{-mmedium-calls} instead.
+
+@item -mmixed-code
+@opindex mmixed-code
+Tweak register allocation to help 16-bit instruction generation.
+This generally has the effect of decreasing the average instruction size
+while increasing the instruction count.
+
+@item -mno-brcc
+@opindex mno-brcc
+This option disables a target-specific pass in arc_reorg to generate BRcc
+instructions.  It has no effect on BRcc generation driven by the combiner
+pass.
+
+@item -mno-millicode
+@opindex mno-millicode
+When optimizing for size (using @option{-Os}), prologues / epilogues that
+have to save / restore a lot of registers are often shortened by using call
+to a special function in libgcc; this is referred to as a millicode call.
+As these calls can pose performance issues, and/or cause linking issues
+when you link in a nonstandard way, this option is provided to turn off
+millicode call generation.
+
+@item -msize-level=@var{level}
+@ opindex msize-level
+Fine-tune size optimization with regards to instruction lengths and alignment.
+The recognized values for @var{level} are:
+@table @samp
+@item 0
+No size optimization.  This level is deprecated and treated like @samp{1}.
+@item 1
+Short instructions are used opportunistically.
+@item 2
+In addition, alignment of loops and of code after barriers are dropped.
+@item 3
+In addition, optional data alignment is dropped, and the option @option{Os} is enabled.
+
+@end table
+
+This defaults to @samp{3} when @option{-Os} is in effect.  Otherwise,
+the behaviour when this is not set is equivalent to level @samp{1}.
+
+@item -multcost=@var{num}
+@opindex multcost
+Cost to assume for a multiply instruction, with @samp{4} being equal to a
+normal instruction.
+
+@item -mindexed-loads
+@opindex mindexed-loads
+Enable the use of indexed loads.  This can be problematic because some
+optimizers will then assume the that indexed stores exist, which is not
+the case.
+
+@item -mauto-modify-reg
+@opindex mauto-modify-reg
+Enable the use of pre/post modify with register displacement.
+
+@item -mold-di-patterns
+@opindex mold-di-patterns
+Enable use of old DI patterns that have presumably been obsoleted by subreg lowering.
+
+@item -munalign-prob-threshold=@var{probability}
+@opindex munalign-prob-threshold
+Set probability threshold for unaligning branches.
+When tuning for @samp{ARC700} and optimizing for speed, branches without
+filled delay slot are preferrably emitted unaligned and long, unless
+profiling indicates that the probability for the branch to be taken
+is below @var{probability}.  @xref{Cross-profiling}.
+The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
+
+@item -malign-call
+@opindex malign-call
+Do alignment optimizations for call instructions.
+
+@item -mRcq
+@opindex mRcq
+Enable Rcq constraint handling - most short code generation depends on this.
+This is the default.
+
+@item -mRcw
+@opindex mRcw
+Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
+This is the default.
+
+@item -mearly-cbranchsi
+@opindex mearly-cbranchsi
+Enable pre-reload use of the cbranchsi pattern.
+
+@item -mbbit-peephole
+@opindex mbbit-peephole
+Enable bbit peephole2.
+
+@item -mcase-vector-pcrel
+@opindex mcase-vector-pcrel
+Use pc-relative switch case tables - this enables case table shortening.
+This is the default for @option{-Os}.
+
+@item -mcompact-casesi
+@opindex mcompact-casesi
+Enable compact casesi pattern.
+This is the default for @option{-Os}.
+
+@item -mq-class
+@opindex mq-class
+Enable 'q' instruction alternatives.
+This is the default for @option{-Os}.
+
+@item -mexpand-adddi
+@opindex mexpand-adddi
+Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc.
+
+@c Assembly annotation options
+@item -misize
+@opindex misize
+Annotate assembler instructions with estimated addresses.
+
+@item -mannotate-align
+@opindex mannotate-align
+Explain what alignment considerations lead to the decision to make an
+instruction short or long.
+
+@end table
+
 @node ARM Options
 @subsection ARM Options
 @cindex ARM options
Index: gcc/testsuite/gcc.dg/torture/pr37868.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/pr37868.c	(revision 2691)
+++ gcc/testsuite/gcc.dg/torture/pr37868.c	(working copy)
@@ -1,6 +1,6 @@ 
 /* { dg-do run } */
 /* { dg-options "-fno-strict-aliasing" } */
-/* { dg-skip-if "unaligned access" { sparc*-*-* sh*-*-* tic6x-*-* } "*" "" } */
+/* { dg-skip-if "unaligned access" { arc*-*-* sparc*-*-* sh*-*-* tic6x-*-* } "*" "" } */
 
 extern void abort (void);
 #if (__SIZEOF_INT__ <= 2)
Index: gcc/testsuite/gcc.dg/stack-usage-1.c
===================================================================
--- gcc/testsuite/gcc.dg/stack-usage-1.c	(revision 2691)
+++ gcc/testsuite/gcc.dg/stack-usage-1.c	(working copy)
@@ -9,6 +9,8 @@ 
 
 #if defined(__aarch64__)
 #  define SIZE 256 /* No frame pointer for leaf functions (default) */
+#elif defined(__arc__)
+#  define SIZE (256-4)
 #elif defined(__i386__)
 #  define SIZE 248
 #elif defined(__x86_64__)
Index: gcc/testsuite/gcc.c-torture/execute/20101011-1.c
===================================================================
--- gcc/testsuite/gcc.c-torture/execute/20101011-1.c	(revision 2691)
+++ gcc/testsuite/gcc.c-torture/execute/20101011-1.c	(working copy)
@@ -40,6 +40,9 @@ 
 #elif defined (__CRIS__)
   /* No SIGFPE for CRIS integer division.  */
 # define DO_TEST 0
+#elif defined (__arc__)
+  /* No SIGFPE for ARC integer division.  */
+# define DO_TEST 0
 #elif defined (__arm__) && defined (__ARM_EABI__)
 # ifdef __ARM_ARCH_EXT_IDIV__
   /* Hardware division instructions may not trap, and handle trapping
Index: libgcc/config.host
===================================================================
--- libgcc/config.host	(revision 2691)
+++ libgcc/config.host	(working copy)
@@ -316,6 +316,14 @@ 
 	extra_parts="$extra_parts vms-dwarf2.o vms-dwarf2eh.o"
 	md_unwind_header=alpha/vms-unwind.h
 	;;
+arc-*-elf*)
+	tmake_file="arc/t-arc-newlib arc/t-arc"
+	extra_parts="crti.o crtn.o crtend.o crtbegin.o crtendS.o crtbeginS.o libgmon.a crtg.o crtgend.o"
+	;;
+arc*-*-linux-uclibc*)
+	tmake_file="${tmake_file} t-slibgcc-libgcc t-slibgcc-nolc-override arc/t-arc700-uClibc arc/t-arc"
+	extra_parts="crti.o crtn.o crtend.o crtbegin.o crtendS.o crtbeginS.o libgmon.a crtg.o crtgend.o"
+	;;
 arm-wrs-vxworks)
 	tmake_file="$tmake_file arm/t-arm arm/t-vxworks t-fdpbit"
 	extra_parts="$extra_parts crti.o crtn.o"
Index: libstdc++-v3/acinclude.m4
===================================================================
--- libstdc++-v3/acinclude.m4	(revision 2691)
+++ libstdc++-v3/acinclude.m4	(working copy)
@@ -2985,6 +2985,8 @@  void foo()
     if AC_TRY_EVAL(ac_compile); then
       if grep _Unwind_SjLj_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=yes
+      elif grep _Unwind_SjLj_Register conftest.s >/dev/null 2>&1 ; then
+	enable_sjlj_exceptions=yes
       elif grep _Unwind_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=no
       elif grep __cxa_end_cleanup conftest.s >/dev/null 2>&1 ; then
Index: libstdc++-v3/configure
===================================================================
--- libstdc++-v3/configure	(revision 2691)
+++ libstdc++-v3/configure	(working copy)
@@ -15051,6 +15051,8 @@  void foo()
   test $ac_status = 0; }; then
       if grep _Unwind_SjLj_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=yes
+      elif grep _Unwind_SjLj_Register conftest.s >/dev/null 2>&1 ; then
+	enable_sjlj_exceptions=yes
       elif grep _Unwind_Resume conftest.s >/dev/null 2>&1 ; then
 	enable_sjlj_exceptions=no
       elif grep __cxa_end_cleanup conftest.s >/dev/null 2>&1 ; then
@@ -15383,7 +15385,7 @@  main ()
   # Fake what AC_TRY_COMPILE does.
 
     cat > conftest.$ac_ext << EOF
-#line 15386 "configure"
+#line 15388 "configure"
 int main()
 {
   typedef bool atomic_type;
@@ -15418,7 +15420,7 @@  int main()
     rm -f conftest*
 
     cat > conftest.$ac_ext << EOF
-#line 15421 "configure"
+#line 15423 "configure"
 int main()
 {
   typedef short atomic_type;
@@ -15453,7 +15455,7 @@  int main()
     rm -f conftest*
 
     cat > conftest.$ac_ext << EOF
-#line 15456 "configure"
+#line 15458 "configure"
 int main()
 {
   // NB: _Atomic_word not necessarily int.
@@ -15489,7 +15491,7 @@  int main()
     rm -f conftest*
 
     cat > conftest.$ac_ext << EOF
-#line 15492 "configure"
+#line 15494 "configure"
 int main()
 {
   typedef long long atomic_type;
@@ -15568,7 +15570,7 @@  int main()
   # unnecessary for this test.
 
     cat > conftest.$ac_ext << EOF
-#line 15571 "configure"
+#line 15573 "configure"
 int main()
 {
   _Decimal32 d1;
@@ -15610,7 +15612,7 @@  int main()
   # unnecessary for this test.
 
     cat > conftest.$ac_ext << EOF
-#line 15613 "configure"
+#line 15615 "configure"
 template<typename T1, typename T2>
   struct same
   { typedef T2 type; };
@@ -15644,7 +15646,7 @@  int main()
     rm -f conftest*
 
     cat > conftest.$ac_ext << EOF
-#line 15647 "configure"
+#line 15649 "configure"
 template<typename T1, typename T2>
   struct same
   { typedef T2 type; };
Index: libstdc++-v3/ChangeLog.ARC
===================================================================
--- libstdc++-v3/ChangeLog.ARC	(revision 0)
+++ libstdc++-v3/ChangeLog.ARC	(revision 2694)
@@ -0,0 +1,5 @@ 
+2012-08-16  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+	* acinclude.m4 (GLIBCXX_ENABLE_SJLJ_EXCEPTIONS): In auto-test,
+	also scan for _Unwind_SjLj_Register.
+	* configure: Regenerate.