Patchwork [2/6] ARM: tegra: Add auxiliary data for nvhost

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Submitter Terje Bergström
Date Nov. 22, 2012, 9:48 a.m.
Message ID <1353577684-7896-3-git-send-email-tbergstrom@nvidia.com>
Download mbox | patch
Permalink /patch/201128/
State Not Applicable, archived
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Comments

Terje Bergström - Nov. 22, 2012, 9:48 a.m.
Add SoC specific auxiliary data to host1x and gr2d. nvhost uses
this data.

Change-Id: Idb04b262c8b6432e56cffb6c7ed64cf7ef4545b3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
---
 arch/arm/mach-tegra/board-dt-tegra20.c    |   38 ++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/board-dt-tegra30.c    |   38 ++++++++++++++++++++++++++++-
 arch/arm/mach-tegra/tegra20_clocks_data.c |    8 +++---
 arch/arm/mach-tegra/tegra30_clocks_data.c |    2 ++
 4 files changed, 80 insertions(+), 6 deletions(-)
Thierry Reding - Nov. 23, 2012, 11:45 p.m.
On Thu, Nov 22, 2012 at 11:48:00AM +0200, Terje Bergstrom wrote:
> Add SoC specific auxiliary data to host1x and gr2d. nvhost uses
> this data.
> 
> Change-Id: Idb04b262c8b6432e56cffb6c7ed64cf7ef4545b3
> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
> ---
>  arch/arm/mach-tegra/board-dt-tegra20.c    |   38 ++++++++++++++++++++++++++++-
>  arch/arm/mach-tegra/board-dt-tegra30.c    |   38 ++++++++++++++++++++++++++++-
>  arch/arm/mach-tegra/tegra20_clocks_data.c |    8 +++---
>  arch/arm/mach-tegra/tegra30_clocks_data.c |    2 ++
>  4 files changed, 80 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
> index 1d30eac..c695392 100644
> --- a/arch/arm/mach-tegra/board-dt-tegra20.c
> +++ b/arch/arm/mach-tegra/board-dt-tegra20.c
> @@ -33,6 +33,7 @@
>  #include <linux/i2c.h>
>  #include <linux/i2c-tegra.h>
>  #include <linux/usb/tegra_usb_phy.h>
> +#include <linux/nvhost.h>
>  
>  #include <asm/hardware/gic.h>
>  #include <asm/mach-types.h>
> @@ -45,6 +46,38 @@
>  #include "common.h"
>  #include "iomap.h"
>  
> +static const char *host1x_syncpt_names[32] = {
> +	[0] = "gfx_host",
> +	[NVSYNCPT_2D_0] = "2d_0",
> +	[NVSYNCPT_2D_1] = "2d_1",
> +	[NVSYNCPT_VBLANK0] = "vblank0",
> +	[NVSYNCPT_VBLANK1] = "vblank1",
> +};

I think I remember a discussion about this back when we designed the DT
bindings. The result I seem to remember was that since syncpoints can be
arbitrarily assigned they wouldn't have to be statically allocated at
compile time.

Instead we could just have them allocated when a host1x client registers
with host1x. Or have each client request its required syncpoints
explicitly. The latter would make it trivial to associate a label with
it.

> +
> +static struct host1x_device_info host1x_info = {
> +	.nb_channels	= 8,
> +	.nb_pts		= 32,
> +	.nb_mlocks	= 16,
> +	.nb_bases	= 8,
> +	.syncpt_names	= host1x_syncpt_names,
> +	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
> +};
> +
> +static struct nvhost_device_data tegra_host1x_info = {
> +	.clocks = { {"host1x", UINT_MAX} },
> +	NVHOST_MODULE_NO_POWERGATE_IDS,
> +	.private_data = &host1x_info,
> +};
> +
> +static struct nvhost_device_data tegra_gr2d_info = {
> +	.index		= 2,
> +	.syncpts	= BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
> +	.clocks		= { {"gr2d", UINT_MAX, true}, {"epp", UINT_MAX, true} },
> +	NVHOST_MODULE_NO_POWERGATE_IDS,
> +	.clockgate_delay = 0,
> +	.serialize	= true,
> +};

Again, this doesn't seem like it should be statically configured in the
board data.

The same comments apply to the Tegra30 hunk that I've left out.

> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
> index 7f049ac..3314e50 100644
> --- a/arch/arm/mach-tegra/tegra20_clocks_data.c
> +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
> @@ -1041,10 +1041,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
>  	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
>  	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
>  	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
> -	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
> -	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
> -	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
> -	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
> +	CLK_DUPLICATE("2d",	NULL,		"gr2d"),
> +	CLK_DUPLICATE("3d",	NULL,		"gr3d"),
> +	CLK_DUPLICATE("epp",	NULL,		"epp"),
> +	CLK_DUPLICATE("mpe",	NULL,		"mpe"),

Are these actually required here?

>  	CLK_DUPLICATE("cop",	"tegra-avp",	"cop"),
>  	CLK_DUPLICATE("vde",	"tegra-aes",	"vde"),
>  	CLK_DUPLICATE("cclk",	NULL,		"cpu"),
> diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
> index 6942c7a..f30bd54 100644
> --- a/arch/arm/mach-tegra/tegra30_clocks_data.c
> +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
> @@ -1338,6 +1338,8 @@ struct clk_duplicate tegra_clk_duplicates[] = {
>  	CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
>  	CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
>  	CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
> +	CLK_DUPLICATE("2d", NULL, "gr2d"),
> +	CLK_DUPLICATE("epp", NULL, "epp"),

Same here.

Thierry
Terje Bergström - Nov. 24, 2012, 7:09 a.m.
On 24.11.2012 01:45, Thierry Reding wrote:
> I think I remember a discussion about this back when we designed the DT
> bindings. The result I seem to remember was that since syncpoints can be
> arbitrarily assigned they wouldn't have to be statically allocated at
> compile time.
> Instead we could just have them allocated when a host1x client registers
> with host1x. Or have each client request its required syncpoints
> explicitly. The latter would make it trivial to associate a label with
> it.

True. I didn't yet have time to implement dynamic allocation and I
didn't want to wait for that to get the code out. I'll try to find time
for that.

> 
>> +
>> +static struct host1x_device_info host1x_info = {
>> +	.nb_channels	= 8,
>> +	.nb_pts		= 32,
>> +	.nb_mlocks	= 16,
>> +	.nb_bases	= 8,
>> +	.syncpt_names	= host1x_syncpt_names,
>> +	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
>> +};
>> +
>> +static struct nvhost_device_data tegra_host1x_info = {
>> +	.clocks = { {"host1x", UINT_MAX} },
>> +	NVHOST_MODULE_NO_POWERGATE_IDS,
>> +	.private_data = &host1x_info,
>> +};
>> +
>> +static struct nvhost_device_data tegra_gr2d_info = {
>> +	.index		= 2,
>> +	.syncpts	= BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
>> +	.clocks		= { {"gr2d", UINT_MAX, true}, {"epp", UINT_MAX, true} },
>> +	NVHOST_MODULE_NO_POWERGATE_IDS,
>> +	.clockgate_delay = 0,
>> +	.serialize	= true,
>> +};
> 
> Again, this doesn't seem like it should be statically configured in the
> board data.

The host1x specifics (number of channels, pts etc) are description of
hardware, so they could go to a device tree binding.

The allocation of sync points is a software policy that could be handled
by the driver.

Clocks are waiting for the general discussion about clock bindings in
device trees, but that data is SoC specific, so that's why I've put that
in board data.

Clock gating policy is software feature that could be in driver.

>> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
>> index 7f049ac..3314e50 100644
>> --- a/arch/arm/mach-tegra/tegra20_clocks_data.c
>> +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
>> @@ -1041,10 +1041,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
>>  	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
>>  	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
>>  	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
>> -	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
>> -	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
>> -	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
>> -	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
>> +	CLK_DUPLICATE("2d",	NULL,		"gr2d"),
>> +	CLK_DUPLICATE("3d",	NULL,		"gr3d"),
>> +	CLK_DUPLICATE("epp",	NULL,		"epp"),
>> +	CLK_DUPLICATE("mpe",	NULL,		"mpe"),
> 
> Are these actually required here?

I think we had problems in driver acquiring the clocks without this
(mismatch of driver), but I could retry. The old bindings assumed that
driver would be called "tegra_grhost", but that's not the case.

Terje
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Thierry Reding - Nov. 24, 2012, 7:11 p.m.
On Sat, Nov 24, 2012 at 09:09:11AM +0200, Terje Bergström wrote:
> On 24.11.2012 01:45, Thierry Reding wrote:
> > I think I remember a discussion about this back when we designed the DT
> > bindings. The result I seem to remember was that since syncpoints can be
> > arbitrarily assigned they wouldn't have to be statically allocated at
> > compile time.
> > Instead we could just have them allocated when a host1x client registers
> > with host1x. Or have each client request its required syncpoints
> > explicitly. The latter would make it trivial to associate a label with
> > it.
> 
> True. I didn't yet have time to implement dynamic allocation and I
> didn't want to wait for that to get the code out. I'll try to find time
> for that.

Okay, sounds good. I agree that it was good to post these patches soon.
The earlier they can be discussed and reviewed the better.

> >> +
> >> +static struct host1x_device_info host1x_info = {
> >> +	.nb_channels	= 8,
> >> +	.nb_pts		= 32,
> >> +	.nb_mlocks	= 16,
> >> +	.nb_bases	= 8,
> >> +	.syncpt_names	= host1x_syncpt_names,
> >> +	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
> >> +};
> >> +
> >> +static struct nvhost_device_data tegra_host1x_info = {
> >> +	.clocks = { {"host1x", UINT_MAX} },
> >> +	NVHOST_MODULE_NO_POWERGATE_IDS,
> >> +	.private_data = &host1x_info,
> >> +};
> >> +
> >> +static struct nvhost_device_data tegra_gr2d_info = {
> >> +	.index		= 2,
> >> +	.syncpts	= BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
> >> +	.clocks		= { {"gr2d", UINT_MAX, true}, {"epp", UINT_MAX, true} },
> >> +	NVHOST_MODULE_NO_POWERGATE_IDS,
> >> +	.clockgate_delay = 0,
> >> +	.serialize	= true,
> >> +};
> > 
> > Again, this doesn't seem like it should be statically configured in the
> > board data.
> 
> The host1x specifics (number of channels, pts etc) are description of
> hardware, so they could go to a device tree binding.

I'm not sure that's even required. The number of syncpoints and channels
should be static for a particular version of SoC, right? In that case it
can be derived from the DT compatible property, can't it?

> The allocation of sync points is a software policy that could be handled
> by the driver.
> 
> Clocks are waiting for the general discussion about clock bindings in
> device trees, but that data is SoC specific, so that's why I've put that
> in board data.
> 
> Clock gating policy is software feature that could be in driver.
> 
> >> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
> >> index 7f049ac..3314e50 100644
> >> --- a/arch/arm/mach-tegra/tegra20_clocks_data.c
> >> +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
> >> @@ -1041,10 +1041,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
> >>  	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
> >>  	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
> >>  	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
> >> -	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
> >> -	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
> >> -	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
> >> -	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
> >> +	CLK_DUPLICATE("2d",	NULL,		"gr2d"),
> >> +	CLK_DUPLICATE("3d",	NULL,		"gr3d"),
> >> +	CLK_DUPLICATE("epp",	NULL,		"epp"),
> >> +	CLK_DUPLICATE("mpe",	NULL,		"mpe"),
> > 
> > Are these actually required here?
> 
> I think we had problems in driver acquiring the clocks without this
> (mismatch of driver), but I could retry. The old bindings assumed that
> driver would be called "tegra_grhost", but that's not the case.

I hope that DT clock support will go into 3.9, in which case the issue
will just go away.

Thierry
Terje Bergström - Nov. 26, 2012, 9:40 a.m.
On 24.11.2012 21:11, Thierry Reding wrote:
> On Sat, Nov 24, 2012 at 09:09:11AM +0200, Terje Bergström wrote:
>> The host1x specifics (number of channels, pts etc) are description of
>> hardware, so they could go to a device tree binding.
> 
> I'm not sure that's even required. The number of syncpoints and channels
> should be static for a particular version of SoC, right? In that case it
> can be derived from the DT compatible property, can't it?

I might be a bit confused here about the purpose of device trees.

The register aperture, irqs and enumerated list of devices could also be
derived from the information about host1x compatibility properly. They
don't change within SoC version. Why do we have them in device tree?

I have considered device trees to be the alternative to being able to
query hardware. As we can't ask the hardware the number of sync points
and channels, we should have them in device trees in the same way as we
have IO apertures and list of client modules.

Terje
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Terje Bergström - Nov. 26, 2012, 1:56 p.m.
On 24.11.2012 21:11, Thierry Reding wrote:
>>>> diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
>>>> index 7f049ac..3314e50 100644
>>>> --- a/arch/arm/mach-tegra/tegra20_clocks_data.c
>>>> +++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
>>>> @@ -1041,10 +1041,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
>>>>  	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
>>>>  	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
>>>>  	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
>>>> -	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
>>>> -	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
>>>> -	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
>>>> -	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
>>>> +	CLK_DUPLICATE("2d",	NULL,		"gr2d"),
>>>> +	CLK_DUPLICATE("3d",	NULL,		"gr3d"),
>>>> +	CLK_DUPLICATE("epp",	NULL,		"epp"),
>>>> +	CLK_DUPLICATE("mpe",	NULL,		"mpe"),
>>>
>>> Are these actually required here?

It looks like the change from tegra_grhost to NULL is required. nvhost
cannot acquire the clock if this change is not done:

[    0.848517] tegra-gr2d tegra-gr2d: Cannot get clock gr2d

But I'll need to stage the aux data and clock changes to separate
patches with explanations.

Terje

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Stephen Warren - Nov. 26, 2012, 10:53 p.m.
On 11/26/2012 02:40 AM, Terje Bergström wrote:
> On 24.11.2012 21:11, Thierry Reding wrote:
>> On Sat, Nov 24, 2012 at 09:09:11AM +0200, Terje Bergström wrote:
>>> The host1x specifics (number of channels, pts etc) are description of
>>> hardware, so they could go to a device tree binding.
>>
>> I'm not sure that's even required. The number of syncpoints and channels
>> should be static for a particular version of SoC, right? In that case it
>> can be derived from the DT compatible property, can't it?
> 
> I might be a bit confused here about the purpose of device trees.
> 
> The register aperture, irqs and enumerated list of devices could also be
> derived from the information about host1x compatibility properly. They
> don't change within SoC version. Why do we have them in device tree?

That's potentially true.

But, consider something like an I2C controller. We have 4 or 5 instances
of that. Each has a different register base, IRQ, etc. Hence, the
per-instance information is in DT. Some HW modules are singleton so
putting req/IRQ in DT might not be strictly necessary, but then the
argument becomes that its better to be consistent and get reg/IRQ from
DT in all cases, not only where strictly necessary.

Another question is: Can we support likely future HW versions just by
changing DT data? If so, putting the data in DT is probably a good
things. Lets say that Tegra20 and Tegra30 host1x are exactly identical
except for a different base address and different # of syncpoint
registers. If we put that information in DT, we don't even need to add a
new compatible value to the driver, nor a new table mapping that
compatible value to the # syncpoints. That means new HW support without
having to write code. There is obviously a trade-off to make in order to
decide exactly what's best to go into DT and what's best to go into the
driver. Something simple like #syncpoints might do well in DT. Something
like the entire Tegra pin controller pin/group/... definitions don't
really make sense to put in DT.
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Patch

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 1d30eac..c695392 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -33,6 +33,7 @@ 
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/nvhost.h>
 
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -45,6 +46,38 @@ 
 #include "common.h"
 #include "iomap.h"
 
+static const char *host1x_syncpt_names[32] = {
+	[0] = "gfx_host",
+	[NVSYNCPT_2D_0] = "2d_0",
+	[NVSYNCPT_2D_1] = "2d_1",
+	[NVSYNCPT_VBLANK0] = "vblank0",
+	[NVSYNCPT_VBLANK1] = "vblank1",
+};
+
+static struct host1x_device_info host1x_info = {
+	.nb_channels	= 8,
+	.nb_pts		= 32,
+	.nb_mlocks	= 16,
+	.nb_bases	= 8,
+	.syncpt_names	= host1x_syncpt_names,
+	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device_data tegra_host1x_info = {
+	.clocks = { {"host1x", UINT_MAX} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+	.private_data = &host1x_info,
+};
+
+static struct nvhost_device_data tegra_gr2d_info = {
+	.index		= 2,
+	.syncpts	= BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+	.clocks		= { {"gr2d", UINT_MAX, true}, {"epp", UINT_MAX, true} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+	.clockgate_delay = 0,
+	.serialize	= true,
+};
+
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
 	.operating_mode = TEGRA_USB_OTG,
 	.power_down_on_bus_suspend = 1,
@@ -94,13 +127,16 @@  struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
-	OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x",
+			&tegra_host1x_info),
 	OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-nand", 0x70008000, "tegra-nand", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-gr2d", 0x54140000, "tegra-gr2d",
+		       &tegra_gr2d_info),
 	{}
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 6497d12..1afa68b 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -29,6 +29,7 @@ 
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/nvhost.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -38,6 +39,38 @@ 
 #include "common.h"
 #include "iomap.h"
 
+static const char *host1x_syncpt_names[32] = {
+	[0] = "gfx_host",
+	[NVSYNCPT_2D_0] = "2d_0",
+	[NVSYNCPT_2D_1] = "2d_1",
+	[NVSYNCPT_VBLANK0] = "vblank0",
+	[NVSYNCPT_VBLANK1] = "vblank1",
+};
+
+static struct host1x_device_info host1x_info = {
+	.nb_channels	= 8,
+	.nb_pts		= 32,
+	.nb_mlocks	= 16,
+	.nb_bases	= 8,
+	.syncpt_names	= host1x_syncpt_names,
+	.client_managed	= NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device_data tegra_host1x_info = {
+	.clocks = { {"host1x", UINT_MAX} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+	.private_data = &host1x_info,
+};
+
+static struct nvhost_device_data tegra_gr2d_info = {
+	.index		= 2,
+	.syncpts	= BIT(NVSYNCPT_2D_0) | BIT(NVSYNCPT_2D_1),
+	.clocks		= { {"gr2d", UINT_MAX, true}, {"epp", UINT_MAX, true} },
+	NVHOST_MODULE_NO_POWERGATE_IDS,
+	.clockgate_delay = 0,
+	.serialize	= true,
+};
+
 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
@@ -57,12 +90,15 @@  struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
-	OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x",
+			&tegra_host1x_info),
 	OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-gr2d", 0x54140000, "gr2d",
+		       &tegra_gr2d_info),
 	{}
 };
 
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index 7f049ac..3314e50 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -1041,10 +1041,10 @@  static struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("usbd",	"utmip-pad",	NULL),
 	CLK_DUPLICATE("usbd",	"tegra-ehci.0",	NULL),
 	CLK_DUPLICATE("usbd",	"tegra-otg",	NULL),
-	CLK_DUPLICATE("2d",	"tegra_grhost",	"gr2d"),
-	CLK_DUPLICATE("3d",	"tegra_grhost",	"gr3d"),
-	CLK_DUPLICATE("epp",	"tegra_grhost",	"epp"),
-	CLK_DUPLICATE("mpe",	"tegra_grhost",	"mpe"),
+	CLK_DUPLICATE("2d",	NULL,		"gr2d"),
+	CLK_DUPLICATE("3d",	NULL,		"gr3d"),
+	CLK_DUPLICATE("epp",	NULL,		"epp"),
+	CLK_DUPLICATE("mpe",	NULL,		"mpe"),
 	CLK_DUPLICATE("cop",	"tegra-avp",	"cop"),
 	CLK_DUPLICATE("vde",	"tegra-aes",	"vde"),
 	CLK_DUPLICATE("cclk",	NULL,		"cpu"),
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index 6942c7a..f30bd54 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1338,6 +1338,8 @@  struct clk_duplicate tegra_clk_duplicates[] = {
 	CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
 	CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
 	CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
+	CLK_DUPLICATE("2d", NULL, "gr2d"),
+	CLK_DUPLICATE("epp", NULL, "epp"),
 };
 
 struct clk *tegra_ptr_clks[] = {