From patchwork Thu Nov 22 13:41:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasanth Ananthan X-Patchwork-Id: 201050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A828E2C0093 for ; Fri, 23 Nov 2012 00:56:10 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0466D4A02E; Thu, 22 Nov 2012 14:55:37 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bKW9jx5A7Pth; Thu, 22 Nov 2012 14:55:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C03A4A030; Thu, 22 Nov 2012 14:55:04 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF3C34A021 for ; Thu, 22 Nov 2012 14:41:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q+C+6utbwyDO for ; Thu, 22 Nov 2012 14:41:37 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id E2D5F4A01B for ; Thu, 22 Nov 2012 14:41:30 +0100 (CET) Received: by mail-da0-f44.google.com with SMTP id z20so722642dae.3 for ; Thu, 22 Nov 2012 05:41:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=fQ5aZWgNviCWjiqIRHqnsxb6Y7XEAV9UdxmG9bwUugw=; b=lEFOS9bbOnt3jhWXfwlsR2GLQctTHMJcgRhdDdwMttJzGwA/kAXMnT9yE5eyhQidNK 5p3ZdIxwZMI+yW/HxryOT6Su2m6grN2xrDaFSzZ2RQUgwg4waPtr0oCqYx4v2f0tuV6A I0nwJu5ag9jH+letx2rn4PpXxI7RGrqz0ea3ZDEV7wfuuGt6ylq4DLIBeMYmvEdoKfmX zY13fhvOwfVmsL58800gkYpfsOYRtSEar9DUx1gB2NMZ23n1CVwHOWKV5wiBgkNGnTXZ P6DmROtM2uN8+o1doAabdEmld+S8zim3ip2WuNwTMniTMS/HGuDPGCjKi7tx9vTVhy6F Qm+w== Received: by 10.69.3.161 with SMTP id bx1mr5016947pbd.91.1353591685975; Thu, 22 Nov 2012 05:41:25 -0800 (PST) Received: from vasanth-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id oi2sm2090091pbb.62.2012.11.22.05.41.23 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 05:41:24 -0800 (PST) From: Vasanth Ananthan To: u-boot@lists.denx.de Date: Thu, 22 Nov 2012 19:11:03 +0530 Message-Id: <1353591666-32490-2-git-send-email-vasanthananthan@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1353591666-32490-1-git-send-email-vasanthananthan@gmail.com> References: <1353591666-32490-1-git-send-email-vasanthananthan@gmail.com> X-Mailman-Approved-At: Thu, 22 Nov 2012 14:54:56 +0100 Cc: Vasanth Ananthan , Vasanth Ananthan Subject: [U-Boot] [PATCH 1/4] Exynos5: Add clock support for SATA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds clock support for SATA Signed-off-by: Vasanth Ananthan --- arch/arm/cpu/armv7/exynos/clock.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 23 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..22b327b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,6 +26,7 @@ #include #include #include +#include /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { @@ -326,6 +327,19 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } +static unsigned long exynos5_get_sata_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + /* + * This clock is used as a input for 1ms timer, so return + * the clock equivalent to 1 MHz + */ + + return CONFIG_SYS_CLK_FREQ / 10; +} + /* exynos5: return uart clock frequency */ static unsigned long exynos5_get_uart_clk(int dev_index) { @@ -963,6 +977,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_sata_clock(void) +{ + if (cpu_is_exynos5()) + return exynos5_get_sata_clk(); + + return -ENOSYS; +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cd12323..182ed95 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -42,5 +42,6 @@ void set_i2s_clk_source(void); int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); +unsigned long get_sata_clk(void); #endif