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[77.102.241.218]) by mx.google.com with ESMTPS id dw4sm4202839wib.1.2012.11.22.04.07.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 04:07:53 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/1] ARM: cache-l2x0: Fix compile time warnings when !CONFIG_OF Date: Thu, 22 Nov 2012 12:07:47 +0000 Message-Id: <1353586067-9989-1-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQktoce4AaPo1cDHFsMw/hH9+8Zv83J7mKnXIn5NOSnrwsVw2+eLTl9xt+RbjJvvnyOuXqdR X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121122_070758_422128_9DDD1CF1 X-CRM114-Status: GOOD ( 14.70 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.41 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Gregory CLEMENT , Russell King , Lee Jones , linus.walleij@stericsson.com, arnd@arndb.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Introduced by: 07bd005ed2457876f653fda12981708d737543df ARM: 7547/1: cache-l2x0: add support for Aurora L2 cache ctrl arch/arm/mm/cache-l2x0.c:37:12: warning: ‘l2_wt_override’ defined but not used arch/arm/mm/cache-l2x0.c:292:22: warning: ‘calc_range_end’ defined but not used arch/arm/mm/cache-l2x0.c:315:13: warning: ‘aurora_pa_range’ defined but not used arch/arm/mm/cache-l2x0.c:328:13: warning: ‘aurora_inv_range’ defined but not used arch/arm/mm/cache-l2x0.c:347:13: warning: ‘aurora_clean_range’ defined but not used arch/arm/mm/cache-l2x0.c:365:13: warning: ‘aurora_flush_range’ defined but not used Cc: Russell King Cc: Gregory CLEMENT Signed-off-by: Lee Jones --- arch/arm/mm/cache-l2x0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index bfb5986..25a9226 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -34,7 +34,6 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock); static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; -static int l2_wt_override; /* Aurora don't have the cache ID register available, so we have to * pass it though the device tree */ @@ -284,6 +283,10 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) raw_spin_unlock_irqrestore(&l2x0_lock, flags); } +#ifdef CONFIG_OF + +static int l2_wt_override; + /* * Note that the end addresses passed to Linux primitives are * noninclusive, while the hardware cache range operations use @@ -375,6 +378,7 @@ static void aurora_flush_range(unsigned long start, unsigned long end) } } } +#endif static void l2x0_disable(void) {